| 2009 |
|---|
| 79 | EE | Jeff L. Cobb,
Kanupriya Gulati,
Sunil P. Khatri:
Robust window-based multi-node technology-independent logic minimization.
ACM Great Lakes Symposium on VLSI 2009: 357-362 |
| 78 | EE | Kalyana C. Bollapalli,
Rajesh Garg,
Kanupriya Gulati,
Sunil P. Khatri:
Low power and high performance sram design using bank-based selective forward body bias.
ACM Great Lakes Symposium on VLSI 2009: 441-444 |
| 77 | EE | Kanupriya Gulati,
Sunil P. Khatri,
Peng Li:
Closed-loop modeling of power and temperature profiles of FPGAs.
FPGA 2009: 287 |
| 76 | EE | Suganth Paul,
Rajesh Garg,
Sunil P. Khatri,
Sheila Vaidya:
Design and implementation of a sub-threshold BFSK transmitter.
ISQED 2009: 664-672 |
| 75 | EE | Rajballav Dash,
Rajesh Garg,
Sunil P. Khatri,
Gwan S. Choi:
SEU hardened clock regeneration circuits.
ISQED 2009: 806-813 |
| 74 | EE | Kanupriya Gulati,
Suganth Paul,
Sunil P. Khatri,
Srinivas Patil,
Abhijit Jas:
FPGA-based hardware acceleration for Boolean satisfiability.
ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
| 2008 |
|---|
| 73 | EE | Arunprasad Venkatraman,
Rajesh Garg,
Sunil P. Khatri:
A robust, fast pulsed flip-flop design.
ACM Great Lakes Symposium on VLSI 2008: 119-122 |
| 72 | EE | Kanupriya Gulati,
Sunil P. Khatri:
Improving FPGA routability using network coding.
ACM Great Lakes Symposium on VLSI 2008: 147-150 |
| 71 | EE | Suganth Paul,
Rajesh Garg,
Sunil P. Khatri:
Pipelined network of PLA based circuit design.
ACM Great Lakes Symposium on VLSI 2008: 213-218 |
| 70 | EE | Salman Gopalani,
Rajesh Garg,
Sunil P. Khatri,
Mosong Cheng:
A lithography-friendly structured ASIC design approach.
ACM Great Lakes Symposium on VLSI 2008: 315-320 |
| 69 | EE | Kanupriya Gulati,
Sunil P. Khatri:
Towards acceleration of fault simulation using graphics processing units.
DAC 2008: 822-827 |
| 68 | EE | Rajesh Garg,
Charu Nagpal,
Sunil P. Khatri:
A fast, analytical estimator for the SEU-induced pulse width in combinational designs.
DAC 2008: 918-923 |
| 67 | EE | Chunjie Duan,
Chengyu Zhu,
Sunil P. Khatri:
Forbidden transition free crosstalk avoidance CODEC design.
DAC 2008: 986-991 |
| 66 | EE | Charu Nagpal,
Rajesh Garg,
Sunil P. Khatri:
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements.
DATE 2008: 354-359 |
| 65 | EE | Chunjie Duan,
Sunil P. Khatri:
Energy Efficient and High Speed On-Chip Ternary Bus.
DATE 2008: 515-518 |
| 64 | EE | Rajesh Garg,
Gagandeep Mallarapu,
Sunil P. Khatri:
A Single-supply True Voltage Level Shifter.
DATE 2008: 979-984 |
| 63 | EE | Victor H. Cordero,
Sunil P. Khatri:
Clock Distribution Scheme using Coplanar Transmission Lines.
DATE 2008: 985-990 |
| 62 | EE | Rajesh Garg,
Sunil P. Khatri:
A novel, highly SEU tolerant digital circuit design approach.
ICCD 2008: 14-20 |
| 61 | EE | Rajesh Garg,
Peng Li,
Sunil P. Khatri:
Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs).
ISCAS 2008: 1788-1791 |
| 60 | EE | Sabyasachi Das,
Sunil P. Khatri:
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters.
VLSI Design 2008: 572-579 |
| 59 | EE | Sabyasachi Das,
Sunil P. Khatri:
A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions.
VLSI Design 2008: 635-640 |
| 58 | EE | Sabyasachi Das,
Sunil P. Khatri:
An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products.
VLSI Design 2008: 653-659 |
| 57 | EE | Nikhil Saluja,
Kanupriya Gulati,
Sunil P. Khatri:
SAT-based ATPG using multilevel compatible don't-cares.
ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
| 56 | EE | Sabyasachi Das,
Sunil P. Khatri:
Resource sharing among mutually exclusive sum-of-product blocks for area reduction.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 55 | EE | Sabyasachi Das,
Sunil P. Khatri:
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.
IEEE Trans. VLSI Syst. 16(3): 326-331 (2008) |
| 54 | EE | A. Kapoor,
Nikhil Jayakumar,
Sunil P. Khatri:
Dynamically De-Skewable Clock Distribution Methodology.
IEEE Trans. VLSI Syst. 16(9): 1220-1229 (2008) |
| 53 | EE | Kanupriya Gulati,
Nikhil Jayakumar,
Sunil P. Khatri,
D. M. H. Walker:
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations.
Integration 41(3): 399-412 (2008) |
| 2007 |
|---|
| 52 | EE | Nikhil Jayakumar,
Sunil P. Khatri:
An algorithm to minimize leakage through simultaneous input vector control and circuit modification.
DATE 2007: 618-623 |
| 51 | EE | Eugene Goldberg,
Kanupriya Gulati,
Sunil P. Khatri:
Toggle Equivalence Preserving (TEP) Logic Optimization.
DSD 2007: 271-279 |
| 50 | EE | Kanupriya Gulati,
Nikhil Jayakumar,
Sunil P. Khatri:
A Structured ASIC Design Approach Using Pass Transistor Logic.
ISCAS 2007: 1787-1790 |
| 49 | EE | Jeff L. Cobb,
Rajesh Garg,
Sunil P. Khatri:
A methodology for interconnect dimension determination.
ISPD 2007: 189-195 |
| 48 | EE | Nikhil Jayakumar,
Sunil P. Khatri:
A Predictably Low-Leakage ASIC Design Style.
IEEE Trans. VLSI Syst. 15(3): 276-285 (2007) |
| 47 | EE | Vijay Nagarajan,
Stefan Laendner,
Nikhil Jayakumar,
Olgica Milenkovic,
Sunil P. Khatri:
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems.
VLSI Signal Processing 49(1): 185-206 (2007) |
| 2006 |
|---|
| 46 | EE | Bo Shen,
Sunil P. Khatri,
Takis Zourntos:
Implementation of MOSFET based capacitors for digital applications.
ACM Great Lakes Symposium on VLSI 2006: 180-186 |
| 45 | EE | Rajesh Garg,
Mario Sanchez,
Kanupriya Gulati,
Nikhil Jayakumar,
Anshul Gupta,
Sunil P. Khatri:
A design flow to optimize circuit delay by using standard cells and PLAs.
ACM Great Lakes Symposium on VLSI 2006: 217-222 |
| 44 | EE | Scott J. Campbell,
Sunil P. Khatri:
Resource and delay efficient matrix multiplication using newer FPGA devices.
ACM Great Lakes Symposium on VLSI 2006: 308-311 |
| 43 | EE | Brock J. LaMeres,
Kanupriya Gulati,
Sunil P. Khatri:
Controlling inductive cross-talk and power in off-chip buses using CODECs.
ASP-DAC 2006: 850-855 |
| 42 | EE | Nikhil Jayakumar,
Rajesh Garg,
Bruce Gamache,
Sunil P. Khatri:
A PLA based asynchronous micropipelining approach for subthreshold circuit design.
DAC 2006: 419-424 |
| 41 | EE | Rajesh Garg,
Nikhil Jayakumar,
Sunil P. Khatri,
Gwan Choi:
A design approach for radiation-hard digital electronics.
DAC 2006: 773-778 |
| 40 | EE | Brock J. LaMeres,
Sunil P. Khatri:
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission.
DATE 2006: 522-527 |
| 39 | EE | Nikhil Jayakumar,
Sunil P. Khatri,
Kanupriya Gulati,
Alexander Sprintson:
Network coding for routability improvement in VLSI.
ICCAD 2006: 820-823 |
| 38 | EE | Mandar Waghmode,
Kanupriya Gulati,
Sunil P. Khatri,
Weiping Shi:
An Efficient, Scalable Hardware Engine for Boolean SATisfiability.
ICCD 2006 |
| 37 | EE | Eric Menendez,
Dumezie Maduike,
Rajesh Garg,
Sunil P. Khatri:
CMOS Comparators for High-Speed and Low-Power Applications.
ICCD 2006 |
| 36 | EE | Rajesh Garg,
Nikhil Jayakumar,
Sunil P. Khatri:
On the Improvement of Statistical Static Timing Analysis.
ICCD 2006 |
| 35 | EE | Kanupriya Gulati,
Nikhil Jayakumar,
Sunil P. Khatri:
A probabilistic method to determine the minimum leakage vector for combinational designs.
ISCAS 2006 |
| 34 | EE | Chunjie Duan,
Sunil P. Khatri:
Computing during supply voltage switching in DVS enabled real-time processors.
ISCAS 2006 |
| 33 | EE | Kanupriya Gulati,
M. Lovell,
Sunil P. Khatri:
Efficient don't care computation for hierarchical designs.
ISCAS 2006 |
| 32 | EE | Rajesh Garg,
Sunil P. Khatri:
Generalized buffering of PTL logic stages using Boolean division.
ISCAS 2006 |
| 31 | EE | Chunjie Duan,
Kanupriya Gulati,
Sunil P. Khatri:
Memory-based crosstalk canceling CODECs for on-chip buses.
ISCAS 2006 |
| 2005 |
|---|
| 30 | EE | Van R. Culver,
Sunil P. Khatri:
A dynamic voltage scaling algorithm for energy reduction in hard real-time systems.
ASP-DAC 2005: 842-845 |
| 29 | EE | Nikhil Jayakumar,
Sandeep Dhar,
Sunil P. Khatri:
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents.
DAC 2005: 43-46 |
| 28 | EE | Nikhil Jayakumar,
Sunil P. Khatri:
A variation tolerant subthreshold design approach.
DAC 2005: 716-719 |
| 27 | EE | Brock J. LaMeres,
Sunil P. Khatri:
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission.
DATE 2005: 1318-1323 |
| 26 | | Ganesh Venkataraman,
Nikhil Jayakumar,
Jiang Hu,
Peng Li,
Sunil P. Khatri,
Anand Rajaram,
Patrick McGuinness,
Charles J. Alpert:
Practical techniques to reduce skew and its variations in buffered clock networks.
ICCAD 2005: 592-596 |
| 25 | EE | Nikhil Jayakumar,
Sunil P. Khatri:
Minimum Energy Near-threshold Network of PLA based Design.
ICCD 2005: 399-404 |
| 24 | EE | Seraj Ahmad,
Nikhil Jayakumar,
Vijay Balasubramanian,
Edward Hursey,
Sunil P. Khatri,
Rabi N. Mahapatra:
X-Routing using Two Manhattan Route Instances.
ICCD 2005: 45-52 |
| 23 | EE | Brock J. LaMeres,
Sunil P. Khatri:
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages.
ICCD 2005: 683-688 |
| 22 | EE | Brock J. LaMeres,
Sunil P. Khatri:
Performance model for inter-chip communication considering inductive cross-talk and cost.
ISCAS (4) 2005: 4130-4133 |
| 21 | EE | Kanupriya Gulati,
Nikhil Jayakumar,
Sunil P. Khatri:
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.
ISLPED 2005: 111-114 |
| 20 | EE | Edward Hursey,
Nikhil Jayakumar,
Sunil P. Khatri:
Non-Manhattan Routing Using a Manhattan Router.
VLSI Design 2005: 445-450 |
| 2004 |
|---|
| 19 | EE | Nikhil Saluja,
Sunil P. Khatri:
A robust algorithm for approximate compatible observability don't care (CODC) computation.
DAC 2004: 422-427 |
| 18 | EE | Chunjie Duan,
Sunil P. Khatri:
Exploiting Crosstalk to Speed up On-Chip Buse.
DATE 2004: 778-783 |
| 17 | EE | Nikhil Jayakumar,
Sunil P. Khatri:
A metal and via maskset programmable VLSI design methodology using PLAs.
ICCAD 2004: 590-594 |
| 16 | EE | A. Kapoor,
Nikhil Jayakumar,
Sunil P. Khatri:
A novel clock distribution and dynamic de-skewing methodology.
ICCAD 2004: 626-631 |
| 15 | EE | Sunil P. Khatri,
Subarnarekha Sinha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
SPFD-based wire removal in standard-cell and network-of-PLA circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1020-1030 (2004) |
| 2003 |
|---|
| 14 | EE | Nikhil Jayakumar,
Sunil P. Khatri:
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.
ISLPED 2003: 128-133 |
| 2002 |
|---|
| 13 | EE | Sabyasachi Das,
Sunil P. Khatri:
An efficient and regular routing methodology for datapath designsusing net regularity extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 93-101 (2002) |
| 2001 |
|---|
| 12 | EE | Wilsin Gosti,
Sunil P. Khatri,
Alberto L. Sangiovanni-Vincentelli:
Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement.
ICCAD 2001: 224-231 |
| 11 | EE | Sabyasachi Das,
Sunil P. Khatri:
A regularity-driven fast gridless detailed router for high frequency datapath designs.
ISPD 2001: 130-135 |
| 2000 |
|---|
| 10 | | Sunil P. Khatri,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric.
ICCAD 2000: 412-418 |
| 9 | EE | Subarnarekha Sinha,
Sunil P. Khatri,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks.
ICCD 2000: 494-503 |
| 1999 |
|---|
| 8 | EE | Sunil P. Khatri,
Amit Mehrotra,
Robert K. Brayton,
Ralph H. J. M. Otten,
Alberto L. Sangiovanni-Vincentelli:
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications.
DAC 1999: 491-496 |
| 7 | | Robert K. Brayton,
Sunil P. Khatri:
Multi-Valued Logic Synthesis.
VLSI Design 1999: 196-105 |
| 6 | EE | Sunil P. Khatri,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Sequential Multi-Valued Network Simplification using Redundancy Removal.
VLSI Design 1999: 206-211 |
| 1996 |
|---|
| 5 | | Robert K. Brayton,
Gary D. Hachtel,
Alberto L. Sangiovanni-Vincentelli,
Fabio Somenzi,
Adnan Aziz,
Szu-Tsung Cheng,
Stephen A. Edwards,
Sunil P. Khatri,
Yuji Kukimoto,
Abelardo Pardo,
Shaz Qadeer,
Rajeev K. Ranjan,
Shaker Sarwary,
Thomas R. Shiple,
Gitanjali Swamy,
Tiziano Villa:
VIS: A System for Verification and Synthesis.
CAV 1996: 428-432 |
| 4 | EE | Sunil P. Khatri,
Amit Narayan,
Sriram C. Krishnan,
Kenneth L. McMillan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Engineering Change in a Non-Deterministic FSM Setting.
DAC 1996: 451-456 |
| 3 | | Robert K. Brayton,
Gary D. Hachtel,
Alberto L. Sangiovanni-Vincentelli,
Fabio Somenzi,
Adnan Aziz,
Szu-Tsung Cheng,
Stephen A. Edwards,
Sunil P. Khatri,
Yuji Kukimoto,
Abelardo Pardo,
Shaz Qadeer,
Rajeev K. Ranjan,
Shaker Sarwary,
Thomas R. Shiple,
Gitanjali Swamy,
Tiziano Villa:
VIS.
FMCAD 1996: 248-256 |
| 2 | | Jawahar Jain,
Amit Narayan,
C. Coelho,
Sunil P. Khatri,
Alberto L. Sangiovanni-Vincentelli,
Robert K. Brayton,
Masahiro Fujita:
Decomposition Techniques for Efficient ROBDD Construction.
FMCAD 1996: 419-434 |
| 1 | EE | Amit Narayan,
Sunil P. Khatri,
Jawahar Jain,
Masahiro Fujita,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A study of composition schemes for mixed apply/compose based construction of ROBDDs.
VLSI Design 1996: 249-253 |
