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Sunil P. Khatri

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2009
79EEJeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri: Robust window-based multi-node technology-independent logic minimization. ACM Great Lakes Symposium on VLSI 2009: 357-362
78EEKalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI 2009: 441-444
77EEKanupriya Gulati, Sunil P. Khatri, Peng Li: Closed-loop modeling of power and temperature profiles of FPGAs. FPGA 2009: 287
76EESuganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya: Design and implementation of a sub-threshold BFSK transmitter. ISQED 2009: 664-672
75EERajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi: SEU hardened clock regeneration circuits. ISQED 2009: 806-813
74EEKanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas: FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
2008
73EEArunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri: A robust, fast pulsed flip-flop design. ACM Great Lakes Symposium on VLSI 2008: 119-122
72EEKanupriya Gulati, Sunil P. Khatri: Improving FPGA routability using network coding. ACM Great Lakes Symposium on VLSI 2008: 147-150
71EESuganth Paul, Rajesh Garg, Sunil P. Khatri: Pipelined network of PLA based circuit design. ACM Great Lakes Symposium on VLSI 2008: 213-218
70EESalman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng: A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI 2008: 315-320
69EEKanupriya Gulati, Sunil P. Khatri: Towards acceleration of fault simulation using graphics processing units. DAC 2008: 822-827
68EERajesh Garg, Charu Nagpal, Sunil P. Khatri: A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC 2008: 918-923
67EEChunjie Duan, Chengyu Zhu, Sunil P. Khatri: Forbidden transition free crosstalk avoidance CODEC design. DAC 2008: 986-991
66EECharu Nagpal, Rajesh Garg, Sunil P. Khatri: A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. DATE 2008: 354-359
65EEChunjie Duan, Sunil P. Khatri: Energy Efficient and High Speed On-Chip Ternary Bus. DATE 2008: 515-518
64EERajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri: A Single-supply True Voltage Level Shifter. DATE 2008: 979-984
63EEVictor H. Cordero, Sunil P. Khatri: Clock Distribution Scheme using Coplanar Transmission Lines. DATE 2008: 985-990
62EERajesh Garg, Sunil P. Khatri: A novel, highly SEU tolerant digital circuit design approach. ICCD 2008: 14-20
61EERajesh Garg, Peng Li, Sunil P. Khatri: Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ISCAS 2008: 1788-1791
60EESabyasachi Das, Sunil P. Khatri: A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. VLSI Design 2008: 572-579
59EESabyasachi Das, Sunil P. Khatri: A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. VLSI Design 2008: 635-640
58EESabyasachi Das, Sunil P. Khatri: An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. VLSI Design 2008: 653-659
57EENikhil Saluja, Kanupriya Gulati, Sunil P. Khatri: SAT-based ATPG using multilevel compatible don't-cares. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
56EESabyasachi Das, Sunil P. Khatri: Resource sharing among mutually exclusive sum-of-product blocks for area reduction. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
55EESabyasachi Das, Sunil P. Khatri: A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. IEEE Trans. VLSI Syst. 16(3): 326-331 (2008)
54EEA. Kapoor, Nikhil Jayakumar, Sunil P. Khatri: Dynamically De-Skewable Clock Distribution Methodology. IEEE Trans. VLSI Syst. 16(9): 1220-1229 (2008)
53EEKanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker: A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration 41(3): 399-412 (2008)
2007
52EENikhil Jayakumar, Sunil P. Khatri: An algorithm to minimize leakage through simultaneous input vector control and circuit modification. DATE 2007: 618-623
51EEEugene Goldberg, Kanupriya Gulati, Sunil P. Khatri: Toggle Equivalence Preserving (TEP) Logic Optimization. DSD 2007: 271-279
50EEKanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A Structured ASIC Design Approach Using Pass Transistor Logic. ISCAS 2007: 1787-1790
49EEJeff L. Cobb, Rajesh Garg, Sunil P. Khatri: A methodology for interconnect dimension determination. ISPD 2007: 189-195
48EENikhil Jayakumar, Sunil P. Khatri: A Predictably Low-Leakage ASIC Design Style. IEEE Trans. VLSI Syst. 15(3): 276-285 (2007)
47EEVijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri: High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. VLSI Signal Processing 49(1): 185-206 (2007)
2006
46EEBo Shen, Sunil P. Khatri, Takis Zourntos: Implementation of MOSFET based capacitors for digital applications. ACM Great Lakes Symposium on VLSI 2006: 180-186
45EERajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri: A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222
44EEScott J. Campbell, Sunil P. Khatri: Resource and delay efficient matrix multiplication using newer FPGA devices. ACM Great Lakes Symposium on VLSI 2006: 308-311
43EEBrock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri: Controlling inductive cross-talk and power in off-chip buses using CODECs. ASP-DAC 2006: 850-855
42EENikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri: A PLA based asynchronous micropipelining approach for subthreshold circuit design. DAC 2006: 419-424
41EERajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi: A design approach for radiation-hard digital electronics. DAC 2006: 773-778
40EEBrock J. LaMeres, Sunil P. Khatri: Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. DATE 2006: 522-527
39EENikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson: Network coding for routability improvement in VLSI. ICCAD 2006: 820-823
38EEMandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi: An Efficient, Scalable Hardware Engine for Boolean SATisfiability. ICCD 2006
37EEEric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri: CMOS Comparators for High-Speed and Low-Power Applications. ICCD 2006
36EERajesh Garg, Nikhil Jayakumar, Sunil P. Khatri: On the Improvement of Statistical Static Timing Analysis. ICCD 2006
35EEKanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A probabilistic method to determine the minimum leakage vector for combinational designs. ISCAS 2006
34EEChunjie Duan, Sunil P. Khatri: Computing during supply voltage switching in DVS enabled real-time processors. ISCAS 2006
33EEKanupriya Gulati, M. Lovell, Sunil P. Khatri: Efficient don't care computation for hierarchical designs. ISCAS 2006
32EERajesh Garg, Sunil P. Khatri: Generalized buffering of PTL logic stages using Boolean division. ISCAS 2006
31EEChunjie Duan, Kanupriya Gulati, Sunil P. Khatri: Memory-based crosstalk canceling CODECs for on-chip buses. ISCAS 2006
2005
30EEVan R. Culver, Sunil P. Khatri: A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. ASP-DAC 2005: 842-845
29EENikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri: A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. DAC 2005: 43-46
28EENikhil Jayakumar, Sunil P. Khatri: A variation tolerant subthreshold design approach. DAC 2005: 716-719
27EEBrock J. LaMeres, Sunil P. Khatri: Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. DATE 2005: 1318-1323
26 Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert: Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596
25EENikhil Jayakumar, Sunil P. Khatri: Minimum Energy Near-threshold Network of PLA based Design. ICCD 2005: 399-404
24EESeraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra: X-Routing using Two Manhattan Route Instances. ICCD 2005: 45-52
23EEBrock J. LaMeres, Sunil P. Khatri: Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. ICCD 2005: 683-688
22EEBrock J. LaMeres, Sunil P. Khatri: Performance model for inter-chip communication considering inductive cross-talk and cost. ISCAS (4) 2005: 4130-4133
21EEKanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. ISLPED 2005: 111-114
20EEEdward Hursey, Nikhil Jayakumar, Sunil P. Khatri: Non-Manhattan Routing Using a Manhattan Router. VLSI Design 2005: 445-450
2004
19EENikhil Saluja, Sunil P. Khatri: A robust algorithm for approximate compatible observability don't care (CODC) computation. DAC 2004: 422-427
18EEChunjie Duan, Sunil P. Khatri: Exploiting Crosstalk to Speed up On-Chip Buse. DATE 2004: 778-783
17EENikhil Jayakumar, Sunil P. Khatri: A metal and via maskset programmable VLSI design methodology using PLAs. ICCAD 2004: 590-594
16EEA. Kapoor, Nikhil Jayakumar, Sunil P. Khatri: A novel clock distribution and dynamic de-skewing methodology. ICCAD 2004: 626-631
15EESunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1020-1030 (2004)
2003
14EENikhil Jayakumar, Sunil P. Khatri: An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. ISLPED 2003: 128-133
2002
13EESabyasachi Das, Sunil P. Khatri: An efficient and regular routing methodology for datapath designsusing net regularity extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 93-101 (2002)
2001
12EEWilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli: Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. ICCAD 2001: 224-231
11EESabyasachi Das, Sunil P. Khatri: A regularity-driven fast gridless detailed router for high frequency datapath designs. ISPD 2001: 130-135
2000
10 Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD 2000: 412-418
9EESubarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. ICCD 2000: 494-503
1999
8EESunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli: A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. DAC 1999: 491-496
7 Robert K. Brayton, Sunil P. Khatri: Multi-Valued Logic Synthesis. VLSI Design 1999: 196-105
6EESunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential Multi-Valued Network Simplification using Redundancy Removal. VLSI Design 1999: 206-211
1996
5 Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS: A System for Verification and Synthesis. CAV 1996: 428-432
4EESunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Engineering Change in a Non-Deterministic FSM Setting. DAC 1996: 451-456
3 Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS. FMCAD 1996: 248-256
2 Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita: Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434
1EEAmit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253

Coauthor Index

1Seraj Ahmad [24]
2Charles J. Alpert [26]
3Adnan Aziz [3] [5]
4Vijay Balasubramanian [24]
5Kalyana C. Bollapalli [78]
6Robert K. Brayton [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [15]
7Scott J. Campbell [44]
8Mosong Cheng [70]
9Szu-Tsung Cheng [3] [5]
10Gwan S. Choi (Gwan Choi) [41] [75]
11Jeff L. Cobb [49] [79]
12C. Coelho [2]
13Victor H. Cordero [63]
14Van R. Culver [30]
15Sabyasachi Das [11] [13] [55] [56] [58] [59] [60]
16Rajballav Dash [75]
17Sandeep Dhar [29]
18Chunjie Duan [18] [31] [34] [65] [67]
19Stephen A. Edwards [3] [5]
20Masahiro Fujita [1] [2]
21Bruce Gamache [42]
22Rajesh Garg [32] [36] [37] [41] [42] [45] [49] [61] [62] [64] [66] [68] [70] [71] [73] [75] [76] [78]
23Eugene Goldberg (Evguenii I. Goldberg) [51]
24Salman Gopalani [70]
25Wilsin Gosti [12]
26Kanupriya Gulati [21] [31] [33] [35] [38] [39] [43] [45] [50] [51] [53] [57] [69] [72] [74] [77] [78] [79]
27Anshul Gupta [45]
28Gary D. Hachtel [3] [5]
29Jiang Hu [26]
30Edward Hursey [20] [24]
31Jawahar Jain [1] [2]
32Abhijit Jas [74]
33Nikhil Jayakumar [14] [16] [17] [20] [21] [24] [25] [26] [28] [29] [35] [36] [39] [41] [42] [45] [47] [48] [50] [52] [53] [54]
34A. Kapoor [16] [54]
35Sriram C. Krishnan [4]
36Yuji Kukimoto [3] [5]
37Brock J. LaMeres [22] [23] [27] [40] [43]
38Stefan Laendner [47]
39Peng Li [26] [61] [77]
40M. Lovell [33]
41Dumezie Maduike [37]
42Rabi N. Mahapatra [24]
43Gagandeep Mallarapu [64]
44Patrick McGuinness [26]
45Kenneth L. McMillan [4]
46Amit Mehrotra [8]
47Eric Menendez [37]
48Olgica Milenkovic [47]
49Vijay Nagarajan [47]
50Charu Nagpal [66] [68]
51Amit Narayan [1] [2] [4]
52Ralph H. J. M. Otten [8]
53Abelardo Pardo [3] [5]
54Srinivas Patil [74]
55Suganth Paul [71] [74] [76]
56Shaz Qadeer [3] [5]
57Anand Rajaram [26]
58Rajeev K. Ranjan [3] [5]
59Nikhil Saluja [19] [57]
60Mario Sanchez [45]
61Alberto L. Sangiovanni-Vincentelli [1] [2] [3] [4] [5] [6] [8] [9] [10] [12] [15]
62Shaker Sarwary [3] [5]
63Bo Shen [46]
64Weiping Shi [38]
65Thomas R. Shiple [3] [5]
66Subarnarekha Sinha [9] [15]
67Fabio Somenzi [3] [5]
68Alexander Sprintson [39]
69Gitanjali Swamy [3] [5]
70Sheila Vaidya [76]
71Ganesh Venkataraman [26]
72Arunprasad Venkatraman [73]
73Tiziano Villa [3] [5]
74Mandar Waghmode [38]
75D. M. H. Walker (Duncan M. Hank Walker) [53]
76Chengyu Zhu [67]
77Takis Zourntos [46]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)