Thomas Wild

2008
19	EE	Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf: A Hardware Packet Re-Sequencer Unit for Network Processors. ARCS 2008: 85-97
18	EE	Andreas Lankes, Thomas Wild, Johannes Zeppenfeld: System Level Simulation of Autonomic SoCs with TAPES. ARCS 2008: 9-22
17	EE	Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf: Buffer allocation for advanced packet segmentation in Network Processors. ASAP 2008: 221-226
16	EE	Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf: Network processors. FPL 2008: 352
15	EE	Zhonglei Wang, Thomas Wild, Stefan Rüping, Bernhard Lippmann: Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design. ISVLSI 2008: 16-21
14	EE	Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf: A Processing Path Dispatcher in Network Processor MPSoCs. IEEE Trans. VLSI Syst. 16(10): 1335-1345 (2008)
2007
13	EE	Andreas Lankes, Thomas Wild, Johannes Zeppenfeld: Power Estimation of Time Variant SoCs with TAPES. DSD 2007: 261-264
12	EE	Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf: A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. ISVLSI 2007: 259-264
11	EE	Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf: Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications. Journal of Systems Architecture 53(10): 703-718 (2007)
2006
10	EE	Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf: Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. DATE 2006: 248-253
9	EE	Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, Thomas Wild: Reconfigurable Processing Units vs. Reconfigurable Interconnects. Dynamically Reconfigurable Architectures 2006
8	EE	Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf: Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. ICSAMOS 2006: 152-159
7	EE	Jürgen Foag, Thomas Wild: Queuing algorithm for speculative Network Processors. IJHPCN 4(5/6): 241-247 (2006)
2005
6	EE	Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild: FlexPath NP: a network processor concept with application-driven flexible processing paths. CODES+ISSS 2005: 279-284
2004
5		Jürgen Foag, Thomas Wild: Queuing Algorithm for Speculative Network Processors. HPCS 2004: 3-8
2003
4	EE	Winthir Brunnbauer, Thomas Wild, Jürgen Foag, Nuria Pazos: A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. DSD 2003: 98-103
3	EE	Thomas Wild, Jürgen Foag, Nuria Pazos, Winthir Brunnbauer: Mapping and Scheduling for Architecture Exploration of Networking SoCs. VLSI Design 2003: 376-381
2002
2	EE	Jürgen Foag, Nuria Pazos, Thomas Wild, Winthir Brunnbauer: Self-Adaptive Parallel Processing Architecture For High-speed Networking. HPCS 2002: 45-52
1	EE	Jürgen Foag, Thomas Wild, Nuria Pazos, Winthir Brunnbauer: Predictive methodology for high-performance networking. ISCC 2002: 169-174

Coauthor Index

1	Carsten Albrecht	[16]
2	Winthir Brunnbauer	[1] [2] [3] [4]
3	Christopher Claus	[9]
4	Jürgen Foag	[1] [2] [3] [4] [5] [7]
5	Andreas Herkersdorf	[6] [8] [9] [10] [11] [12] [14] [16] [17] [19]
6	Kimon Karras	[17]
7	Roman Koch	[16]
8	Andreas Lankes	[13] [18]
9	Bernhard Lippmann	[15]
10	Daniel Llorente	[17]
11	Erik Maehle	[16]
12	Michael Meitinger	[8] [9] [11] [12] [14] [16] [19]
13	Rainer Ohlendorf	[6] [8] [9] [10] [11] [12] [14] [16] [19]
14	Nuria Pazos	[1] [2] [3] [4]
15	Thilo Pionteck	[16]
16	Holm Rauchfuss	[8] [11]
17	Stefan Rüping	[15]
18	Zhonglei Wang	[15]
19	Johannes Zeppenfeld	[13] [18]