2008 |
7 | EE | Rouwaida Kanj,
Rajiv V. Joshi,
Zhou Li,
Jente B. Kuang,
Hung C. Ngo,
Ying Zhou,
Weiping Shi,
Sani R. Nassif:
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
ISLPED 2008: 87-92 |
6 | EE | Jente B. Kuang,
Keunwoo Kim,
Ching-Te Chuang,
Hung C. Ngo,
F. H. Gebara,
Kevin J. Nowka:
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.
IEEE Trans. VLSI Syst. 16(12): 1657-1665 (2008) |
2006 |
5 | EE | Jayakumaran Sivagnaname,
Hung C. Ngo,
Kevin J. Nowka,
Robert K. Montoye,
Richard B. Brown:
Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.
VLSI Design 2006: 89-93 |
4 | EE | Wendy Belluomini,
Damir Jamsek,
Andrew K. Martin,
Chandler McDowell,
Robert K. Montoye,
Hung C. Ngo,
Jun Sawada:
Limited switch dynamic logic circuits for high-speed low-power circuit design.
IBM Journal of Research and Development 50(2-3): 277-286 (2006) |
2005 |
3 | EE | Jente B. Kuang,
Hung C. Ngo,
Kevin J. Nowka,
J. C. Law,
Rajiv V. Joshi:
A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.
ICCD 2005: 574-584 |
2 | EE | Jayakumaran Sivagnaname,
Hung C. Ngo,
Kevin J. Nowka,
Robert K. Montoye,
Richard B. Brown:
Controlled-Load Limited Switch Dynamic Logic Circuit.
ISQED 2005: 83-87 |
2004 |
1 | | Ramyanshu Datta,
Jacob A. Abraham,
Robert K. Montoye,
Wendy Belluomini,
Hung C. Ngo,
Chandler McDowell,
Jente B. Kuang,
Kevin J. Nowka:
A low latency and low power dynamic Carry Save Adder.
ISCAS (2) 2004: 477-480 |