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José L. Núñez-Yáñez

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2008
11EEXiaolin Chen, Cedric Nishan Canagarajah, Raffaele Vitulli, José L. Núñez-Yáñez: Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. ARC 2008: 332-337
10EEXiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, R. M. Goodall: A Novel Delta Sigma Control System Processor and Its VLSI Implementation. IEEE Trans. VLSI Syst. 16(3): 217-228 (2008)
9EEVassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, D. Reisis, K. Nakos, K. Manolopoulos: Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study. Integration 41(1): 135-152 (2008)
2007
8EEJosé L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler: Dynamic Voltage Scaling in a FPGA-based System-on-Chip. FPL 2007: 459-462
7EER. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan: On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS 2007: 3002-3005
2006
6EEXiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova: A Novel Processor Architecture for Real-Time Control. Asia-Pacific Computer Systems Architecture Conference 2006: 270-280
2005
5EETom R. Jacobs, José L. Núñez-Yáñez: A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor. ASAP 2005: 405-410
4EEJosé L. Núñez-Yáñez, Vassilios A. Chouliaras: Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. ASAP 2005: 411-416
3EEVassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez: Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. ISVLSI 2005: 272-273
2 K. Koutsomyti, S. R. Parr, Vassilios A. Chouliaras, José L. Núñez-Yáñez: Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards. SIP 2005: 39-44
1EEJosé L. Núñez-Yáñez, Vassilios A. Chouliaras: A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding. IEEE Trans. Computers 54(11): 1345-1359 (2005)

Coauthor Index

1Shahrukh Agha [9]
2Cedric Nishan Canagarajah [11]
3Xiaolin Chen [11]
4Vassilios A. Chouliaras [1] [2] [3] [4] [6] [8] [9] [10]
5Vincent M. Dwyer [9]
6Jiri Gaisler [8]
7R. M. Goodall [10]
8Roger Goodall [6]
9Tom R. Jacobs [3] [5]
10K. Koutsomyti [2]
11Ashwin K. Kumaraswamy [3]
12K. Maharatna [7]
13K. Manolopoulos [9]
14Jimson Mathew [7]
15K. Nakos [9]
16S. R. Parr [2]
17Dhiraj K. Pradhan [7]
18D. Reisis [9]
19R. Stapenhurst [7]
20Raffaele Vitulli [11]
21Tanya Vladimirova [6]
22Xiaofeng Wu [6] [10]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)