| 2008 |
|---|
| 10 | EE | Huifei Rao,
Jie Chen,
V. H. Zhao,
Woon Tiong Ang,
I-Chyn Wey,
An-Yeu Wu:
An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation.
ISCAS 2008: 608-611 |
| 9 | EE | I-Chyn Wey,
You-Gang Chen,
An-Yeu Wu:
Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits.
IEEE Trans. VLSI Syst. 16(12): 1708-1712 (2008) |
| 2007 |
|---|
| 8 | EE | Huifei Rao,
Jie Chen,
Changhong Yu,
Woon Tiong Ang,
I-Chyn Wey,
An-Yeu Wu,
Hong Zhao:
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design.
ISCAS 2007: 1803-1806 |
| 7 | EE | Jhao-Ji Ye,
You-Gang Chen,
I-Chyn Wey,
An-Yeu Wu:
Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules.
ISCAS 2007: 869-872 |
| 2006 |
|---|
| 6 | EE | Chia-Tsun Wu,
Wei Wang,
I-Chyn Wey,
An-Yeu Wu:
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time.
ISCAS 2006 |
| 5 | EE | Wei Wang,
I-Chyn Wey,
Chia-Tsun Wu,
An-Yeu Wu:
A portable all-digital pulsewidth control loop for SOC applications.
ISCAS 2006 |
| 2005 |
|---|
| 4 | EE | I-Chyn Wey,
Lung-Hao Chang,
You-Gang Chen,
Shih-Hung Chang,
An-Yeu Wu:
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications.
ISCAS (2) 2005: 1074-1077 |
| 3 | EE | Chia-Tsun Wu,
Wei Wang,
I-Chyn Wey,
An-Yeu Wu:
A scalable DCO design for portable ADPLL designs.
ISCAS (6) 2005: 5449-5452 |
| 2003 |
|---|
| 2 | EE | Hwang-Cherng Chow,
I-Chyn Wey:
A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder.
ISCAS (5) 2003: 121-124 |
| 2002 |
|---|
| 1 | EE | Hwang-Cherng Chow,
I-Chyn Wey:
A 3.3 V 1 GHz high speed pipelined Booth multiplier.
ISCAS (1) 2002: 457-460 |
