Chung-Ho Chen

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32EEYi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen: Address compression for scalable load/store queue implementation. ISCAS 2008: 1680-1683
31EETai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: A hybrid self-testing methodology of processor cores. ISCAS 2008: 3378-3381
30EEWei-Cheng Lin, Chung-Ho Chen: Avoiding unnecessary frame memory access and multi-frame motion estimation computation in H.264/AVC. ISCAS 2008: 632-635
29EEYi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen: Power-efficient and scalable load/store queue design via address compression. SAC 2008: 1523-1527
28EETai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: A hybrid software-based self-testing methodology for embedded processor. SAC 2008: 1528-1534
27EEWei-Cheng Lin, Chung-Ho Chen: Frame Buffer Access Reduction for MPEG Video Decoder. IEEE Trans. Circuits Syst. Video Techn. 18(10): 1452-1456 (2008)
26EEChung-Ming Chen, Chung-Ho Chen: Configurable VLSI Architecture for Deblocking Filter in H.264/AVC. IEEE Trans. VLSI Syst. 16(8): 1072-1082 (2008)
25EEWei-Cheng Lin, Chung-Ho Chen: Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG Video Encoder. ICCCN 2007: 817-820
24EEChung-Ho Chen, Min-Tsai Lai: Determining the optimum process mean based on quadratic quality loss function and rectifying inspection plan. European Journal of Operational Research 182(2): 755-763 (2007)
23EEChung-Ho Chen, Min-Tsai Lai: Economic manufacturing quantity, optimum process mean, and economic specification limits setting under the rectifying inspection plan. European Journal of Operational Research 183(1): 336-344 (2007)
22EEChung-Ho Chen, Kuo-Su Hsiao: Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality. IEEE Trans. Computers 56(11): 1534-1548 (2007)
21EEChung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao: Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. IEEE Trans. VLSI Syst. 15(5): 505-517 (2007)
20EEChung-Ming Chen, Chung-Ho Chen: An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC. IEICE Transactions 90-D(1): 99-107 (2007)
19EEKuo-Su Hsiao, Chung-Ho Chen: Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling. ICCD 2006
18EEWei-Cheng Lin, Chung-Ho Chen: Exploring reusable frame buffer data for MPEG-4 video decoding. ISCAS 2006
17EEChung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, Han-Chiang Chen: Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator. LCN 2006: 257-263
16EEChao-Yu Chou, Chun-Hua Chen, Chung-Ho Chen: Economic design of variable sampling intervals T2 control charts using genetic algorithms. Expert Syst. Appl. 30(2): 233-242 (2006)
15 Chung-Ming Chen, Chung-Ho Chen: An efficient VLSI architecture for edge filtering in H.264/AVC. Circuits, Signals, and Systems 2005: 118-122
14 Chung-Ming Chen, Chung-Ho Chen: An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding. Computer Graphics and Imaging 2005: 177-181
13EEKuo-Su Hsiao, Chung-Ho Chen: An efficient wakeup design for energy reduction in high-performance superscalar processors. Conf. Computing Frontiers 2005: 353-360
12EEMing-Chih Chen, Ing-Jer Huang, Chung-Ho Chen: Parameterized MAC unit implementation. ASP-DAC 2001: 23-24
11EEMing-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo: A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17(3): 445-461 (2001)
10 Chung-Ho Chen, Arun K. Somani: Fault Containment in Cache Memories for TMR Redundant Processor Systems. IEEE Trans. Computers 48(4): 386-397 (1999)
9 Chung-Ho Chen, Feng-Fu Lin: An Easy-to-Use Approach for Practical Bus-Based System Design. IEEE Trans. Computers 48(8): 780-793 (1999)
8EEChung-Ho Chen, Akida Wu: Microarchitecture Support for Improving the Performance of Load Target Prediction. MICRO 1997: 228-234
7 Chung-Ho Chen, Arun K. Somani: Architecture Technique Trade-Offs Using Mean Memory Delay Time. IEEE Trans. Computers 45(10): 1089-1100 (1996)
6EECraig M. Wittenbrink, Arun K. Somani, Chung-Ho Chen: Cache write generate for parallel image processing on shared memory architectures. IEEE Transactions on Image Processing 5(7): 1204-1208 (1996)
5 Chung-Ho Chen, Arun K. Somani: A Cache Protocol for Error Detection and Recovery in Fault-Tolerant Computing Systems. FTCS 1994: 278-287
4 Chung-Ho Chen, Arun K. Somani: A Unified Architectural Tradeoff Methodology. ISCA 1994: 348-357
3 Chung-Ho Chen, Arun K. Somani: Effects of Cache Traffic on Shared Bus Multiprocessor Systems. ICPP (1) 1992: 285-288
2 Arun K. Somani, Craig M. Wittenbrink, Robert M. Haralick, Linda G. Shapiro, Jenq-Neng Hwang, Chung-Ho Chen, Robert Johnson, Kenneth Cooper: Proteus System Architecture and Organization. IPPS 1991: 287-294
1 Chung-Ho Chen: An Algebraic Model of Arithmetic Codes. IEEE Trans. Computers 31(4): 318-321 (1982)

Coauthor Index

1Chun-Hua Chen [16]
2Chung-Ming Chen [14] [15] [20] [26]
3Han-Chiang Chen [17]
4Ming-Chih Chen [12]
5Chao-Yu Chou [16]
6Yi-Cheng Chung [17]
7Kenneth Cooper [2]
8Hsun-Wei Gao [21]
9Robert M. Haralick [2]
10Kuo-Su Hsiao [13] [19] [22]
11Chia-Jung Hsu [29] [32]
12Ing-Jer Huang [12]
13Jenq-Neng Hwang [2]
14Robert Johnson [2]
15Min-Tsai Lai [23] [24]
16Kuen-Jong Lee [28] [31]
17Feng-Fu Lin [9]
18Wei-Cheng Lin [18] [25] [27] [30]
19Hsin-Fu Lo [11]
20Tai-Hua Lu [21] [28] [31]
21Linda G. Shapiro [2]
22Ming-Hwa Sheu [11]
23Ming-Der Shieh [11]
24Arun K. Somani [2] [3] [4] [5] [6] [7] [10]
25Yi-Ying Tsai [29] [32]
26Chen-Hua Wang [17]
27Chih-Kai Wei [21]
28Craig M. Wittenbrink [2] [6]
29Akida Wu [8]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)