2008 | ||
---|---|---|
41 | EE | Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Coarse-grained reconfiguration. FPL 2008: 349 |
40 | EE | Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll: Application-specific reconfigurable processors. FPL 2008: 350 |
39 | EE | Peter Zipf: Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays. IEEE Trans. VLSI Syst. 16(2): 134-143 (2008) |
2007 | ||
38 | EE | Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll: A Power Estimation Model for an FPGA-based Softcore Processor. FPL 2007: 171-176 |
37 | Heiko Hinkelmann, Tudor Murgan, G. Liu, Peter Zipf, Manfred Glesner: On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. ReCoSoC 2007: 185-191 | |
36 | Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner: A Customizable LEON2-Based VLIW Processor. ReCoSoC 2007: 55-60 | |
35 | EE | Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck: Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). it - Information Technology 49(3): 174- (2007) |
2006 | ||
34 | EE | Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Design Concepts for a Dynamically ReconfigurableWireless Sensor Node. AHS 2006: 436-441 |
33 | EE | Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner: Implementation of Realtime and Highspeed Phase Detector on FPGA. ARC 2006: 1-11 |
32 | Heiko Hinkelmann, Peter Zipf, Manfred Glesner: A metric for the energy-efficiency of dynamically reconfigurable systems. ARCS Workshops 2006: 152-161 | |
31 | EE | Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner: A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. DATE 2006: 632-637 |
30 | EE | Peter Zipf, Manfred Glesner: Towards an Automated Design of Application-specific Reconfigurable Logic. Dynamically Reconfigurable Architectures 2006 |
29 | EE | Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner: Multitasking Support for Dynamically Reconfig Urable Systems. FPL 2006: 1-6 |
28 | Heiko Hinkelmann, Peter Zipf, Manfred Glesner: A Concept for a Profile-based Dynamic Reconfiguration Mechanism. ReCoSoC 2006: 105-110 | |
2005 | ||
27 | EE | Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio: CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP 2005: 260-267 |
26 | Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner: Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. FPL 2005: 329-334 | |
25 | Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner: A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. FPL 2005: 335-340 | |
24 | Peter Zipf, Oliver Soffke, Michael Velten, Manfred Glesner: Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC. GI Jahrestagung (1) 2005: 329-333 | |
23 | Clemens Schlachta, Oliver Soffke, Peter Zipf, Manfred Glesner: Eine weiterentwickelte quasi-statische adiabatische Logikfamilie. GI Jahrestagung (1) 2005: 448 | |
22 | EE | A. Petrov, Tudor Murgan, Peter Zipf, Manfred Glesner: Functional modeling techniques for a wireless LAN OFDM transceiver. ISCAS (4) 2005: 3970-3973 |
21 | Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel: Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. ReCoSoC 2005: 151-156 | |
20 | Peter Zipf, Claude Stötzler, Manfred Glesner: Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. ReCoSoC 2005: 53-58 | |
19 | EE | Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf: Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS 2005: 12-21 |
2004 | ||
18 | EE | Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan: Reconfigurable platforms for ubiquitous computing. Conf. Computing Frontiers 2004: 377-389 |
17 | EE | Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner: Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers 2004: 404-418 |
16 | EE | Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong: IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. FPL 2004: 526-535 |
15 | EE | Mihail Petrov, Tudor Murgan, F. May, Martin Vorbach, Peter Zipf, Manfred Glesner: The XPP Architecture and Its Co-simulation Within the Simulink Environment. FPL 2004: 761-770 |
14 | Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner: Dynamic power optimization of the trace-back process for the Viterbi algorithm. ISCAS (2) 2004: 721-724 | |
13 | EE | Peter Zipf, Claude Stötzler, Manfred Glesner: A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. ISVLSI 2004: 266-267 |
12 | EE | Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner: A switch architecture and signal synchronization for GALS system-on-chips. SBCCI 2004: 210-215 |
2003 | ||
11 | Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf: IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003 Technische Universität Darmstadt, Insitute of Microelectronic Systems 2003 | |
10 | EE | Stephan Bingemer, Peter Zipf, Manfred Glesner: A granularity-based classification model for systems-on-a-chip. FPGA 2003: 239 |
9 | EE | Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek: Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. FPL 2003: 1111-1114 |
8 | Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner: An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. VLSI-SOC 2003: 167- | |
7 | Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner: A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. VLSI-SOC 2003: 44-49 | |
6 | Stephan Bingemer, Peter Zipf, Manfred Glesner: An Integrated Model Bridging the Gap between Technology and Economy. VLSI-SOC 2003: 442- | |
2002 | ||
5 | Manfred Glesner, Peter Zipf, Michel Renovell: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings Springer 2002 | |
4 | EE | Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner: Fly - A Modifiable Hardware Compiler. FPL 2002: 381-390 |
3 | EE | Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner: A Framework for Teaching (Re)Configurable Architectures in Student Projects. FPL 2002: 444-451 |
2 | EE | Peter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak: Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. FPL 2002: 586-595 |
2000 | ||
1 | EE | Christine Bauer, Peter Zipf, Hans Wojtkowiak: System Design with Genetic Algorithms. FPL 2000: 250-259 |