2008 |
19 | EE | Tzung-Rung Jung,
Lan-Da Van,
Teng-Yao Sheu,
Cheng-Wei Lin,
Wai-Chi Fang:
Design of multi-mode depth buffer compression for 3D graphics system.
ICME 2008: 789-792 |
18 | EE | Chih-Wen Hsueh,
Jen-Feng Chung,
Lan-Da Van,
Chin-Teng Lin:
Anticipatory access pipeline design for phased cache.
ISCAS 2008: 2342-2345 |
17 | EE | Chun-Chieh Huang,
Shao-Hang Hung,
Jen-Feng Chung,
Lan-Da Van,
Chin-Teng Lin:
Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition.
ISCAS 2008: 2717-2720 |
16 | EE | Tzung-Rung Jung,
Lan-Da Van,
Wai-Chi Fang,
Teng-Yao Sheu:
Reconfigurable Depth Buffer Compression Design for 3D Graphics System.
MUE 2008: 470-474 |
15 | EE | Di-You Wu,
Lan-Da Van:
A Grouped-Iterative Framework for MIMO Detection.
VTC Fall 2008: 1-5 |
14 | EE | Chin-Teng Lin,
Yuan-Chu Yu,
Lan-Da Van:
Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor.
IEEE Trans. VLSI Syst. 16(8): 1058-1071 (2008) |
2007 |
13 | EE | Chin-Teng Lin,
Li-Wei Ko,
Ken-Li Lin,
Sheng-Fu Liang,
Bor-Chen Kuo,
I-Fang Chung,
Lan-Da Van:
Classification of Driver's Cognitive Responses Using Nonparametric Single-trial EEG Analysis.
ISCAS 2007: 2019-2023 |
12 | EE | Min-An Song,
Lan-Da Van,
Sy-Yen Kuo:
Adaptive Low-Error Fixed-Width Booth Multipliers.
IEICE Transactions 90-A(6): 1180-1187 (2007) |
11 | EE | Lan-Da Van,
Chin-Teng Lin,
Yuan-Chu Yu:
VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design.
IEICE Transactions 90-A(8): 1644-1652 (2007) |
2006 |
10 | EE | Lan-Da Van,
Hsin-Fu Luo,
Nien-Hsiang Chang,
Chun-Ming Huang:
A cost-effective reconfigurable accelerator for platform-based SOC design.
ISCAS 2006 |
9 | EE | Chin-Teng Lin,
Yuan-Chu Yu,
Lan-Da Van:
A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application.
ISCAS 2006 |
2005 |
8 | EE | Hong-Yu Chao,
Jia-Shung Wang,
Juin-Long Lin,
Kai-Chao Yang,
Chien-Ming Wu,
Chun-Ming Huang,
Lan-Da Van:
High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS.
ICME 2005: 89-92 |
7 | EE | Min-An Song,
Lan-Da Van,
Chih-Chyau Yang,
Shih-Chieh Chiu,
Sy-Yen Kuo:
A framework for the design of error-aware power-efficient fixed-width Booth multipliers.
ISCAS (1) 2005: 81-84 |
2004 |
6 | | Lan-Da Van,
Hsin-Fu Luo,
Chien-Ming Wu,
Wen-Hsiang Hu,
Chun-Ming Huang,
Wei-Chang Tsai:
A high-performance area-aware DSP processor architecture for video codecs.
ICME 2004: 1499-1502 |
5 | EE | Lan-Da Van,
Chih-Chyau Yang:
High-speed area-efficient recursive DFT/IDFT architectures.
ISCAS (3) 2004: 357-360 |
2002 |
4 | EE | Lan-Da Van,
Chih-Hong Chang:
Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR).
ISCAS (1) 2002: 37-40 |
3 | EE | Lan-Da Van,
Sung-Huang Lee:
A generalized methodology for lower-error area-efficient fixed-width multipliers.
ISCAS (1) 2002: 65-68 |
2001 |
2 | EE | Chih-Chun Tang,
Wen-Shih Lu,
Lan-Da Van,
Wu-Shiung Feng:
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage.
ISCAS (4) 2001: 794-797 |
1999 |
1 | EE | Lan-Da Van,
Shuenn-Shyang Wang,
Shing Tenqchen,
Wu-Shiung Feng,
Bor-Shenn Jeng:
Design of a lower-error fixed-width multiplier for speech processing application.
ISCAS (3) 1999: 130-133 |