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Shanq-Jang Ruan

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2008
33EEJui-Yuan Hsieh, Shanq-Jang Ruan: Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm. ASP-DAC 2008: 316-321
32EEShanq-Jang Ruan, Chi-Yu Wu, Jui-Yuan Hsieh: Low Power Design of Precomputation-Based Content-Addressable Memory. IEEE Trans. VLSI Syst. 16(3): 331-335 (2008)
31EEShanq-Jang Ruan, Shang-Fang Tsai: DS2IS: Dictionary-based segmented inversion scheme for low power dynamic bus design. Journal of Systems Architecture - Embedded Systems Design 54(1-2): 324-334 (2008)
2007
30EEShanq-Jang Ruan, Wei-Te Lin: Bipartition Architecture for Low Power JPEG Huffman Decoder. Asia-Pacific Computer Systems Architecture Conference 2007: 235-243
29EEYen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan: Improve CAM power efficiency using decoupled match line scheme. DATE 2007: 165-170
28EEShanq-Jang Ruan, Shang-Fang Tsai, Yu-Ting Pai: Design and Analysis of Low Power Dynamic Bus Based on RLC simulation. ISVLSI 2007: 113-118
27EEYu-Ting Pai, Shanq-Jang Ruan: A High Quality Robust Digital Watermarking by Smart Distribution Technique and Effective Embedded Scheme. IEICE Transactions 90-A(3): 597-605 (2007)
2006
26EEShang-Fang Tsai, Shanq-Jang Ruan: DS2IS: Dictionary-based Segmented Signal Inversion Scheme for Low Power Dynamic Bus Design. ICIT 2006: 293-296
25EEYu-Ting Pai, Shanq-Jang Ruan, Mon-Chau Shie, Yi-Chi Liu: A Simple and Accurate Color Face Detection Algorithm in Complex Background. ICME 2006: 1545-1548
24EEKun-Lin Tsai, Ju-Yueh Lee, Shanq-Jang Ruan, Feipei Lai: Low power scheduling method using multiple supply voltages. ISCAS 2006
23EEShanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen: Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. ISPD 2006: 114-119
22EEYu-Ting Pai, Shanq-Jang Ruan, Jürgen Götze: A High Quality Robust Watermarking Scheme. PCM 2006: 650-657
21EEEdwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn: Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing. IEEE Trans. VLSI Syst. 14(4): 421-425 (2006)
20EEYu-Ting Pai, Shanq-Jang Ruan: Low Power Block-Based Watermarking Algorithm. IEICE Transactions 89-D(4): 1507-1514 (2006)
2005
19EEShanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn: Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design. IPDPS 2005
18EEShanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn: An efficient algorithm for simultaneous wire permutation, inversion, and spacing. ISCAS (1) 2005: 109-112
17EEKun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan: A low power scheduling method using dual V/sub dd/ and dual V/sub th/. ISCAS (1) 2005: 684-687
16EEYu-Ting Pai, Shanq-Jang Ruan, Jürgen Götze: Energy-Efficient Watermark Algorithm Based on Pairing Mechanism. KES (1) 2005: 1219-1225
15EEShanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai: Bipartitioning and encoding in low-power pipelined circuits. ACM Trans. Design Autom. Electr. Syst. 10(1): 24-32 (2005)
14EEChi-Chia Sung, Shanq-Jang Ruan, Bo-Yao Lin, Mon-Chau Shie: Quality and Power Efficient Architecture for the Discrete Cosine Transform. IEICE Transactions 88-A(12): 3500-3507 (2005)
2003
13EEKun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung: State Reordering for Low Power Combinational Logic. Asia-Pacific Computer Systems Architecture Conference 2003: 268-276
12EEEdwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu: On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms. ISCAS (5) 2003: 277-280
11EEYen-Jen Chang, Shanq-Jang Ruan, Feipei Lai: Design and analysis of low-power cache using two-level filter scheme. IEEE Trans. VLSI Syst. 11(4): 568-580 (2003)
2002
10EEShanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai: Energy analysis of bipartition architecture for pipelined circuits. APCCAS (2) 2002: 7-11
9EEShanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai: Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. ICCD 2002: 327-
8EEYen-Jen Chang, Feipei Lai, Shanq-Jang Ruan: Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. ICCD 2002: 334-339
7 Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan: An Efficient Two-Level Filter Scheme for Low Power Cache. IWLS 2002: 61-66
6EEShanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn: ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. IEEE Trans. VLSI Syst. 10(6): 942-949 (2002)
2001
5EEPo-Hung Chen, Shanq-Jang Ruan, Kuen-Pin Wu, Dai-Xun Hu, Feipei Lai, Kun-Lin Tsai: An entropy-based algorithm to reduce area overhead for bipartition-codec architecture. ISCAS (5) 2001: 49-52
4EEShanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Kun-Lin Tsai, Feipei Lai: Synthesis of partition-codec architecture for low power and small area circuit design. ISCAS (5) 2001: 523-526
3EEShanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai: A bipartition-codec architecture to reduce power in pipelinedcircuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 343-348 (2001)
2000
2EEKuen-Pin Wu, Shanq-Jang Ruan, Feipei Lai, Chih-Kuang Tseng: On Key Distribution in Secure Multicasting. LCN 2000: 208-212
1999
1EEShanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang: A bipartition-codec architecture to reduce power in pipelined circuits. ICCAD 1999: 84-90

Coauthor Index

1Yen-Jen Chang [6] [7] [8] [10] [11] [29]
2Szu-Wei Chaung [13] [17]
3Chun-Chih Chen [23]
4Po-Hung Chen [4] [5]
5Shyh-Jong Chen [1]
6Jürgen Götze [16] [22]
7Chia-Lin Ho [9] [10]
8Jui-Yuan Hsieh [32] [33]
9Dai-Xun Hu [5]
10Xian-Jun Huang [1]
11Feipei Lai [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [15] [17] [24]
12Ju-Yueh Lee [24]
13Yuan-Hong Liao [29]
14Bo-Yao Lin [14]
15Jen-Chiun Lin [4]
16Wei-Te Lin [30]
17Le-Chin Liu [12]
18Yi-Chi Liu [25]
19Edwin Naroska [6] [9] [10] [12] [15] [18] [19] [21] [23]
20Yu-Ting Pai [16] [20] [22] [25] [27] [28]
21Uwe Schwiegelshohn [6] [12] [18] [19] [21]
22Rung-Ji Shang [1] [3]
23Mon-Chau Shie [14] [25]
24Chi-Chia Sung [14]
25Kun-Lin Tsai [3] [4] [5] [13] [15] [17] [24]
26Shang-Fang Tsai [26] [28] [31]
27Chih-Kuang Tseng [2]
28Chi-Yu Wu [32]
29Kuen-Pin Wu [2] [5]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)