| 2008 |
|---|
| 33 | EE | Jui-Yuan Hsieh,
Shanq-Jang Ruan:
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm.
ASP-DAC 2008: 316-321 |
| 32 | EE | Shanq-Jang Ruan,
Chi-Yu Wu,
Jui-Yuan Hsieh:
Low Power Design of Precomputation-Based Content-Addressable Memory.
IEEE Trans. VLSI Syst. 16(3): 331-335 (2008) |
| 31 | EE | Shanq-Jang Ruan,
Shang-Fang Tsai:
DS2IS: Dictionary-based segmented inversion scheme for low power dynamic bus design.
Journal of Systems Architecture - Embedded Systems Design 54(1-2): 324-334 (2008) |
| 2007 |
|---|
| 30 | EE | Shanq-Jang Ruan,
Wei-Te Lin:
Bipartition Architecture for Low Power JPEG Huffman Decoder.
Asia-Pacific Computer Systems Architecture Conference 2007: 235-243 |
| 29 | EE | Yen-Jen Chang,
Yuan-Hong Liao,
Shanq-Jang Ruan:
Improve CAM power efficiency using decoupled match line scheme.
DATE 2007: 165-170 |
| 28 | EE | Shanq-Jang Ruan,
Shang-Fang Tsai,
Yu-Ting Pai:
Design and Analysis of Low Power Dynamic Bus Based on RLC simulation.
ISVLSI 2007: 113-118 |
| 27 | EE | Yu-Ting Pai,
Shanq-Jang Ruan:
A High Quality Robust Digital Watermarking by Smart Distribution Technique and Effective Embedded Scheme.
IEICE Transactions 90-A(3): 597-605 (2007) |
| 2006 |
|---|
| 26 | EE | Shang-Fang Tsai,
Shanq-Jang Ruan:
DS2IS: Dictionary-based Segmented Signal Inversion Scheme for Low Power Dynamic Bus Design.
ICIT 2006: 293-296 |
| 25 | EE | Yu-Ting Pai,
Shanq-Jang Ruan,
Mon-Chau Shie,
Yi-Chi Liu:
A Simple and Accurate Color Face Detection Algorithm in Complex Background.
ICME 2006: 1545-1548 |
| 24 | EE | Kun-Lin Tsai,
Ju-Yueh Lee,
Shanq-Jang Ruan,
Feipei Lai:
Low power scheduling method using multiple supply voltages.
ISCAS 2006 |
| 23 | EE | Shanq-Jang Ruan,
Edwin Naroska,
Chun-Chih Chen:
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs.
ISPD 2006: 114-119 |
| 22 | EE | Yu-Ting Pai,
Shanq-Jang Ruan,
Jürgen Götze:
A High Quality Robust Watermarking Scheme.
PCM 2006: 650-657 |
| 21 | EE | Edwin Naroska,
Shanq-Jang Ruan,
Uwe Schwiegelshohn:
Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing.
IEEE Trans. VLSI Syst. 14(4): 421-425 (2006) |
| 20 | EE | Yu-Ting Pai,
Shanq-Jang Ruan:
Low Power Block-Based Watermarking Algorithm.
IEICE Transactions 89-D(4): 1507-1514 (2006) |
| 2005 |
|---|
| 19 | EE | Shanq-Jang Ruan,
Edwin Naroska,
Uwe Schwiegelshohn:
Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design.
IPDPS 2005 |
| 18 | EE | Shanq-Jang Ruan,
Edwin Naroska,
Uwe Schwiegelshohn:
An efficient algorithm for simultaneous wire permutation, inversion, and spacing.
ISCAS (1) 2005: 109-112 |
| 17 | EE | Kun-Lin Tsai,
Szu-Wei Chaung,
Feipei Lai,
Shanq-Jang Ruan:
A low power scheduling method using dual V/sub dd/ and dual V/sub th/.
ISCAS (1) 2005: 684-687 |
| 16 | EE | Yu-Ting Pai,
Shanq-Jang Ruan,
Jürgen Götze:
Energy-Efficient Watermark Algorithm Based on Pairing Mechanism.
KES (1) 2005: 1219-1225 |
| 15 | EE | Shanq-Jang Ruan,
Kun-Lin Tsai,
Edwin Naroska,
Feipei Lai:
Bipartitioning and encoding in low-power pipelined circuits.
ACM Trans. Design Autom. Electr. Syst. 10(1): 24-32 (2005) |
| 14 | EE | Chi-Chia Sung,
Shanq-Jang Ruan,
Bo-Yao Lin,
Mon-Chau Shie:
Quality and Power Efficient Architecture for the Discrete Cosine Transform.
IEICE Transactions 88-A(12): 3500-3507 (2005) |
| 2003 |
|---|
| 13 | EE | Kun-Lin Tsai,
Feipei Lai,
Shanq-Jang Ruan,
Szu-Wei Chaung:
State Reordering for Low Power Combinational Logic.
Asia-Pacific Computer Systems Architecture Conference 2003: 268-276 |
| 12 | EE | Edwin Naroska,
Shanq-Jang Ruan,
Feipei Lai,
Uwe Schwiegelshohn,
Le-Chin Liu:
On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms.
ISCAS (5) 2003: 277-280 |
| 11 | EE | Yen-Jen Chang,
Shanq-Jang Ruan,
Feipei Lai:
Design and analysis of low-power cache using two-level filter scheme.
IEEE Trans. VLSI Syst. 11(4): 568-580 (2003) |
| 2002 |
|---|
| 10 | EE | Shanq-Jang Ruan,
Edwin Naroska,
Yen-Jen Chang,
Chia-Lin Ho,
Feipei Lai:
Energy analysis of bipartition architecture for pipelined circuits.
APCCAS (2) 2002: 7-11 |
| 9 | EE | Shanq-Jang Ruan,
Edwin Naroska,
Chia-Lin Ho,
Feipei Lai:
Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits.
ICCD 2002: 327- |
| 8 | EE | Yen-Jen Chang,
Feipei Lai,
Shanq-Jang Ruan:
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost.
ICCD 2002: 334-339 |
| 7 | | Yen-Jen Chang,
Feipei Lai,
Shanq-Jang Ruan:
An Efficient Two-Level Filter Scheme for Low Power Cache.
IWLS 2002: 61-66 |
| 6 | EE | Shanq-Jang Ruan,
Edwin Naroska,
Yen-Jen Chang,
Feipei Lai,
Uwe Schwiegelshohn:
ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits.
IEEE Trans. VLSI Syst. 10(6): 942-949 (2002) |
| 2001 |
|---|
| 5 | EE | Po-Hung Chen,
Shanq-Jang Ruan,
Kuen-Pin Wu,
Dai-Xun Hu,
Feipei Lai,
Kun-Lin Tsai:
An entropy-based algorithm to reduce area overhead for bipartition-codec architecture.
ISCAS (5) 2001: 49-52 |
| 4 | EE | Shanq-Jang Ruan,
Jen-Chiun Lin,
Po-Hung Chen,
Kun-Lin Tsai,
Feipei Lai:
Synthesis of partition-codec architecture for low power and small area circuit design.
ISCAS (5) 2001: 523-526 |
| 3 | EE | Shanq-Jang Ruan,
Rung-Ji Shang,
Feipei Lai,
Kun-Lin Tsai:
A bipartition-codec architecture to reduce power in pipelinedcircuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 343-348 (2001) |
| 2000 |
|---|
| 2 | EE | Kuen-Pin Wu,
Shanq-Jang Ruan,
Feipei Lai,
Chih-Kuang Tseng:
On Key Distribution in Secure Multicasting.
LCN 2000: 208-212 |
| 1999 |
|---|
| 1 | EE | Shanq-Jang Ruan,
Rung-Ji Shang,
Feipei Lai,
Shyh-Jong Chen,
Xian-Jun Huang:
A bipartition-codec architecture to reduce power in pipelined circuits.
ICCAD 1999: 84-90 |
