2009 | ||
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28 | EE | Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra Yavatkar, Shih-Lien Lu, Nader Bagherzadeh: Low power adaptive pipeline based on instruction isolation. ISQED 2009: 788-793 |
2008 | ||
27 | EE | Changjian Gao, Shih-Lien Lu: Novel FPGA based Haar classifier face detection algorithm acceleration. FPL 2008: 373-378 |
26 | EE | Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu: Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. ISCA 2008: 203-214 |
25 | EE | Shih-Lien Lu, Ravichandran Ramachandran: Carry Logic. Wiley Encyclopedia of Computer Science and Engineering 2008 |
24 | EE | Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu: Active Cache Emulator. IEEE Trans. VLSI Syst. 16(3): 229-240 (2008) |
23 | EE | Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow: A Desktop Computer with a Reconfigurable Pentium®. TRETS 1(1): (2008) |
2007 | ||
22 | EE | Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh: An FPGA-based Pentium in a complete desktop system. FPGA 2007: 53-59 |
21 | EE | Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee: An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. FPL 2007: 47-53 |
20 | EE | Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu: Improving the reliability of on-chip data caches under process variations. ICCD 2007: 325-332 |
19 | EE | Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy: Fine-Grained Redundancy in Adders. ISQED 2007: 317-321 |
18 | EE | John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic: RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27(2): 46-57 (2007) |
2006 | ||
17 | EE | Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu: Design, implementation, and verification of active cache emulator (ACE). FPGA 2006: 63-72 |
2005 | ||
16 | EE | Chunrong Lai, Shih-Lien Lu, Yurong Chen, Trista Chen: Improving branch prediction accuracy with parallel conservative correctors. Conf. Computing Frontiers 2005: 334-341 |
15 | EE | Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu: Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. ICS 2005: 12-20 |
2004 | ||
14 | EE | Chunrong Lai, Shih-Lien Lu: Efficient Victim Mechanism on Sector Cache Organization. Asia-Pacific Computer Systems Architecture Conference 2004: 16-29 |
13 | EE | Shih-Lien Lu: Speeding Up Processing with Approximation Circuits. IEEE Computer 37(3): 67-73 (2004) |
2003 | ||
12 | EE | Shih-Lien Lu, Konrad Lai: Implementation of HW$im - A Real-Time Configurable Cache Simulator. FPL 2003: 638-647 |
11 | EE | Shih-Chang Lai, Shih-Lien Lu: Hardware-based Pointer Data Prefetcher. ICCD 2003: 290-298 |
2002 | ||
10 | EE | Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir: Ditto Processor. DSN 2002: 525-536 |
9 | EE | Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai: Bloom filtering cache misses for accurate data speculation and prefetching. ICS 2002: 189-198 |
8 | EE | Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai: Dynamic addressing memory arrays with physical locality. MICRO 2002: 161-170 |
2000 | ||
7 | EE | Tong Liu, Shih-Lien Lu: Performance improvement with circuit-level speculation. MICRO 2000: 348-355 |
1998 | ||
6 | EE | Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu: Non-Stalling CounterFlow Architecture. HPCA 1998: 334-341 |
1997 | ||
5 | EE | Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller: Advances of the Counterflow Pipeline Microarchitecture. HPCA 1997: 230-236 |
1996 | ||
4 | EE | Ravichandran Ramachandran, Shih-Lien Lu: Efficient arithmetic using self-timing. IEEE Trans. VLSI Syst. 4(4): 445-454 (1996) |
1995 | ||
3 | EE | Shih-Lien Lu: Implementation of micropipelines in enable/disable CMOS differential logic. IEEE Trans. VLSI Syst. 3(2): 338-341 (1995) |
2 | EE | Chih-Ming Chang, Shih-Lien Lu: Design of a static MIMD data flow processor using micropipelines. IEEE Trans. VLSI Syst. 3(3): 370-378 (1995) |
1988 | ||
1 | EE | Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu: Device and circuit simulation interface for an integrated VLSI design environment. IEEE Trans. on CAD of Integrated Circuits and Systems 7(9): 998-1004 (1988) |