| |
| 2008 | ||
|---|---|---|
| 1 | EE | K. Takeuchi, A. Yoshikawa, M. Komoda, K. Kotani, H. Matsushita, Y. Katsuki, Y. Yamamoto, T. Sato: Clock-Skew Test Module for Exploring Reliable Clock-Distribution Under Process and Global Voltage-Temperature Variations. IEEE Trans. VLSI Syst. 16(11): 1559-1566 (2008) |
| 1 | Y. Katsuki | [1] |
| 2 | M. Komoda | [1] |
| 3 | K. Kotani | [1] |
| 4 | T. Sato | [1] |
| 5 | K. Takeuchi | [1] |
| 6 | Y. Yamamoto | [1] |
| 7 | A. Yoshikawa | [1] |