Dinesh Pamunuwa

2008
17	EE	Dinesh Pamunuwa: Memory Technology for Extended Large-Scale Integration in Future Electronics Applications. DATE 2008: 1126-1127
16	EE	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. VLSI Syst. 16(5): 589-593 (2008)
2007
15	EE	Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD 2007: 212-219
14	EE	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design 2007: 308-313
2006
13	EE	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP 2006: 113-120
2005
12	EE	Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS 2005: 277-285
11	EE	Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen: Modeling delay and noise in arbitrarily coupled RC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1725-1739 (2005)
2004
10	EE	Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen: A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integration 38(1): 3-17 (2004)
2003
9	EE	Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen: Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. ICCAD 2003: 835-842
8	EE	Dinesh Pamunuwa, Shauki Elassaad: Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees. ISCAS (4) 2003: 604-607
7	EE	Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: A global wire planning scheme for Network-on-Chip. ISCAS (4) 2003: 892-895
6		Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch: Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. VLSI-SOC 2003: 362-
5	EE	Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Maximizing throughput over parallel wire structures in the deep submicrometer regime. IEEE Trans. VLSI Syst. 11(2): 224-243 (2003)
2002
4	EE	Hannu Tenhunen, Dinesh Pamunuwa: On dynamic delay and repeater insertion. ISCAS (1) 2002: 97-100
3	EE	Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Optimising bandwidth over deep sub-micron interconnect. ISCAS (4) 2002: 193-196
2	EE	Dinesh Pamunuwa, Hannu Tenhunen: On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. ISQED 2002: 240-245
2001
1	EE	Dinesh Pamunuwa, Hannu Tenhunen: Repeater Insertion To Minimise Delay In Coupled Interconnects. VLSI Design 2001: 513-517

Coauthor Index

1	Shauki Elassaad	[8] [9] [11]
2	Axel Jantsch	[6] [10]
3	Jian Liu	[7]
4	Mikael Millberg	[6] [10]
5	Johnny Öberg	[6] [10]
6	Hannu Tenhunen	[1] [2] [3] [4] [5] [7] [9] [10] [11] [12] [13] [14] [15] [16]
7	Roshan Weerasekera	[12] [13] [14] [15] [16]
8	Li-Rong Zheng	[3] [5] [6] [7] [10] [12] [13] [14] [15] [16]