| 2008 |
|---|
| 11 | EE | Julien Lamoureux,
Guy G. Lemieux,
Steven J. E. Wilton:
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering.
IEEE Trans. VLSI Syst. 16(11): 1521-1534 (2008) |
| 10 | EE | Julien Lamoureux,
Steven J. E. Wilton:
On the trade-off between power and flexibility of FPGA clock networks.
TRETS 1(3): (2008) |
| 2007 |
|---|
| 9 | EE | Julien Lamoureux,
Guy G. Lemieux,
Steven J. E. Wilton:
GlitchLess: an active glitch minimization technique for FPGAs.
FPGA 2007: 156-165 |
| 8 | EE | Julien Lamoureux,
Steven J. E. Wilton:
Clock-Aware Placement for FPGAs.
FPL 2007: 124-131 |
| 2006 |
|---|
| 7 | EE | Julien Lamoureux,
Steven J. E. Wilton:
FPGA clock network architecture: flexibility vs. area and power.
FPGA 2006: 101-108 |
| 6 | EE | Julien Lamoureux,
Steven J. E. Wilton:
Architecture and CAD for FPGA Clock Networks.
FPL 2006: 1-2 |
| 5 | EE | Julien Lamoureux,
Steven J. E. Wilton:
Activity Estimation for Field-Programmable Gate Arrays.
FPL 2006: 1-8 |
| 2005 |
|---|
| 4 | EE | Julien Lamoureux,
Steven J. E. Wilton:
On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays.
J. Low Power Electronics 1(2): 119-132 (2005) |
| 2004 |
|---|
| 3 | | Steven J. E. Wilton,
Christopher W. Jones,
Julien Lamoureux:
An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array.
ISCAS (2) 2004: 885-888 |
| 2003 |
|---|
| 2 | EE | Julien Lamoureux,
Steven J. E. Wilton:
On the Interaction Between Power-Aware FPGA CAD Algorithms.
ICCAD 2003: 701-708 |
| 2001 |
|---|
| 1 | EE | Natalia Kazakova,
R. Sung,
Nelson G. Durdle,
Martin Margala,
Julien Lamoureux:
Fast and low-power inner product processor.
ISCAS (4) 2001: 646-649 |
