| 2009 |
|---|
| 88 | EE | Torsten Kempf,
Stefan Wallentowitz,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios.
VLSI Design 2009: 281-286 |
| 87 | EE | Anupam Chattopadhyay,
Harold Ishebabi,
Xiaolin Chen,
Z. Rakosi,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embedded Comput. Syst. 8(2): (2009) |
| 86 | EE | Manuel Hohenauer,
Felix Engel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
A SIMD optimization framework for retargetable compilers.
TACO 6(1): (2009) |
| 2008 |
|---|
| 85 | EE | Lei Gao,
Kingshuk Karuri,
Stefan Kraemer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Multiprocessor performance estimation using hybrid simulation.
DAC 2008: 325-330 |
| 84 | EE | Jianjiang Ceng,
Jerónimo Castrillón,
Weihua Sheng,
Hanno Scharwächter,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Tsuyoshi Isshiki,
Hiroaki Kunieda:
MAPS: an integrated framework for MPSoC application parallelization.
DAC 2008: 754-759 |
| 83 | EE | Anupam Chattopadhyay,
Xiaolin Chen,
Harold Ishebabi,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.
DATE 2008: 1334-1339 |
| 82 | EE | Manuel Hohenauer,
Felix Engel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gerrit Bette,
Balpreet Singh:
Retargetable Code Optimization for Predicated Execution.
DATE 2008: 1492-1497 |
| 81 | EE | Rainer Leupers,
Gerd Ascheid,
Wilfried Verachtert,
Tom Ashby,
Arnout Vandecappelle:
System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures.
DATE 2008 |
| 80 | EE | Anupam Chattopadhyay,
Harold Ishebabi,
Xiaolin Chen,
Z. Rakosi,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embedded Comput. Syst. 7(4): (2008) |
| 79 | EE | Kingshuk Karuri,
Anupam Chattopadhyay,
Xiaolin Chen,
David Kammler,
Ling Hao,
Rainer Leupers,
Heinrich Meyr,
Gerd Ascheid:
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.
IEEE Trans. VLSI Syst. 16(10): 1281-1294 (2008) |
| 78 | EE | Andreas Wieferink,
Tim Kogel,
Olaf Zerres,
Rainer Leupers,
Heinrich Meyr:
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends.
IJES 3(3): 109-118 (2008) |
| 77 | EE | Tim Kogel,
Malte Doerper,
Torsten Kempf,
Andreas Wieferink,
Rainer Leupers,
Heinrich Meyr:
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips.
IJES 3(3): 150-159 (2008) |
| 76 | EE | Diandian Zhang,
Anupam Chattopadhyay,
David Kammler,
Ernst Martin Witte,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
Power-efficient Instruction Encoding Optimization for Various Architecture Classes.
JCP 3(3): 25-38 (2008) |
| 2007 |
|---|
| 75 | EE | Lei Gao,
Stefan Kraemer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
A fast and generic hybrid simulation approach using C virtual machine.
CASES 2007: 3-12 |
| 74 | EE | Hanno Scharwächter,
Jonghee M. Yoon,
Rainer Leupers,
Yunheung Paek,
Gerd Ascheid,
Heinrich Meyr:
A code-generator generator for multi-output instructions.
CODES+ISSS 2007: 131-136 |
| 73 | EE | Stefan Kraemer,
Lei Gao,
Jan Weinstock,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
HySim: a fast simulation framework for embedded software development.
CODES+ISSS 2007: 75-80 |
| 72 | EE | Stefan Kraemer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.
DATE 2007: 1349-1354 |
| 71 | EE | Anupam Chattopadhyay,
W. Ahmed,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Design space exploration of partially re-configurable embedded processors.
DATE 2007: 319-324 |
| 70 | EE | Kingshuk Karuri,
Anupam Chattopadhyay,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Increasing data-bandwidth to instruction-set extensions through register clustering.
ICCAD 2007: 166-171 |
| 69 | EE | Anupam Chattopadhyay,
Z. Rakosi,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
IEEE International Workshop on Rapid System Prototyping 2007: 189-194 |
| 68 | EE | Hanno Scharwächter,
David Kammler,
Andreas Wieferink,
Manuel Hohenauer,
Kingshuk Karuri,
Jianjiang Ceng,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
ASIP architecture exploration for efficient IPSec encryption: A case study.
ACM Trans. Embedded Comput. Syst. 6(2): (2007) |
| 2006 |
|---|
| 67 | EE | Manuel Hohenauer,
Christoph Schumacher,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Hans van Someren:
Retargetable code optimization with SIMD instructions.
CODES+ISSS 2006: 148-153 |
| 66 | EE | Pier Stanislao Paolucci,
Ahmed Amine Jerraya,
Rainer Leupers,
Lothar Thiele,
Piero Vicini:
SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.
CODES+ISSS 2006: 167-172 |
| 65 | EE | Federico Angiolini,
Jianjiang Ceng,
Rainer Leupers,
Federico Ferrari,
Cesare Ferri,
Luca Benini:
An integrated open framework for heterogeneous MPSoC design space exploration.
DATE 2006: 1145-1150 |
| 64 | EE | Torsten Kempf,
Kingshuk Karuri,
Stefan Wallentowitz,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
A SW performance estimation framework for early system-level-design using fine-grained instrumentation.
DATE 2006: 468-473 |
| 63 | EE | Rainer Leupers,
Kingshuk Karuri,
Stefan Kraemer,
M. Pandey:
A design flow for configurable embedded processors based on optimized instruction set extension synthesis.
DATE 2006: 581-586 |
| 62 | EE | Anupam Chattopadhyay,
B. Geukes,
David Kammler,
Ernst Martin Witte,
Oliver Schliebusch,
Harold Ishebabi,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Automatic ADL-based operand isolation for embedded processors.
DATE 2006: 600-605 |
| 61 | EE | Hanno Scharwächter,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
An interprocedural code optimization technique for network processors using hardware multi-threading support.
DATE 2006: 919-924 |
| 60 | EE | Kingshuk Karuri,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Monu Kedia:
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.
DATE Designers' Forum 2006: 221-226 |
| 59 | EE | Luca Fanucci,
Michele Cassiano,
Sergio Saponara,
David Kammler,
Ernst Martin Witte,
Oliver Schliebusch,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
ASIP design and synthesis for non linear filtering in image processing.
DATE Designers' Forum 2006: 233-238 |
| 58 | EE | Kingshuk Karuri,
Christian Huben,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Memory Access Micro-Profiling for ASIP Design.
DELTA 2006: 255-262 |
| 57 | EE | Anupam Chattopadhyay,
Arnab Sinha,
Diandian Zhang,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Integrated Verification Approach during ADL-Driven Processor Design.
IEEE International Workshop on Rapid System Prototyping 2006: 110-118 |
| 56 | EE | Desiree Ottoni,
Guilherme Ottoni,
Guido Araujo,
Rainer Leupers:
Offset assignment using simultaneous variable coalescing.
ACM Trans. Embedded Comput. Syst. 5(4): 864-883 (2006) |
| 55 | EE | Jianjiang Ceng,
Weihua Sheng,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
VLSI Signal Processing 43(2-3): 235-246 (2006) |
| 2005 |
|---|
| 54 | EE | Mohammad Mostafizur Rahman Mozumdar,
Kingshuk Karuri,
Anupam Chattopadhyay,
Stefan Kraemer,
Hanno Scharwächter,
Heinrich Meyr,
Gerd Ascheid,
Rainer Leupers:
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
ASAP 2005: 154-160 |
| 53 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
David Kammler,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr,
Tim Kogel:
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
ASP-DAC 2005: 280-285 |
| 52 | EE | Andreas Wieferink,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Tom Michiels,
Achim Nohl,
Tim Kogel:
Retargetable generation of TLM bus interfaces for MP-SoC platforms.
CODES+ISSS 2005: 249-254 |
| 51 | EE | Kingshuk Karuri,
Mohammad Abdullah Al Faruque,
Stefan Kraemer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Fine-grained application source code profiling for ASIP design.
DAC 2005: 329-334 |
| 50 | EE | Jianjiang Ceng,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun:
C Compiler Retargeting Based on Instruction Semantics Models.
DATE 2005: 1150-1155 |
| 49 | EE | Torsten Kempf,
Malte Doerper,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Tim Kogel,
Bart Vanthournout:
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.
DATE 2005: 876-881 |
| 48 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
Ernst Martin Witte,
David Kammler,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
Optimization Techniques for ADL-Driven RTL Processor Synthesis.
IEEE International Workshop on Rapid System Prototyping 2005: 165-171 |
| 47 | | Rainer Leupers,
Gerd Ascheid:
Digital Signal Processors.
Handbook of Networked and Embedded Control Systems 2005: 279-294 |
| 2004 |
|---|
| 46 | EE | Markus Lorenz,
Peter Marwedel,
Thorsten Dräger,
Gerhard Fettweis,
Rainer Leupers:
Compiler based exploration of DSP energy savings by SIMD operations.
ASP-DAC 2004: 838-841 |
| 45 | EE | Gunnar Braun,
Achim Nohl,
Weihua Sheng,
Jianjiang Ceng,
Manuel Hohenauer,
Hanno Scharwächter,
Rainer Leupers,
Heinrich Meyr:
A novel approach for flexible and consistent ADL-driven ASIP design.
DAC 2004: 717-722 |
| 44 | EE | Andreas Wieferink,
Tim Kogel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun,
Achim Nohl:
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.
DATE 2004: 1256-1263 |
| 43 | EE | Manuel Hohenauer,
Hanno Scharwächter,
Kingshuk Karuri,
Oliver Wahlen,
Tim Kogel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun,
Hans van Someren:
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.
DATE 2004: 1276-1283 |
| 42 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Mario Steinert,
Gunnar Braun,
Achim Nohl:
RTL Processor Synthesis for Architecture Exploration and Implementation.
DATE 2004: 156-160 |
| 41 | EE | Tim Kogel,
Malte Doerper,
Torsten Kempf,
Andreas Wieferink,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.
SAMOS 2004: 138-148 |
| 40 | EE | Andreas Wieferink,
Malte Doerper,
Tim Kogel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Early ISS Integration into Network-on-Chip Designs.
SAMOS 2004: 443-452 |
| 39 | EE | Jianjiang Ceng,
Weihua Sheng,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
SAMOS 2004: 463-473 |
| 38 | EE | Hanno Scharwächter,
David Kammler,
Andreas Wieferink,
Manuel Hohenauer,
Kingshuk Karuri,
Jianjiang Ceng,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.
SCOPES 2004: 33-46 |
| 37 | EE | Gunnar Braun,
Achim Nohl,
Andreas Hoffmann,
Oliver Schliebusch,
Rainer Leupers,
Heinrich Meyr:
A universal technique for fast and flexible instruction-set architecture simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1625-1639 (2004) |
| 2003 |
|---|
| 36 | EE | Rainer Leupers:
Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms.
CC 2003: 290-302 |
| 35 | EE | Tim Kogel,
Malte Doerper,
Andreas Wieferink,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Serge Goossens:
A modular simulation framework for architectural exploration of on-chip interconnection networks.
CODES+ISSS 2003: 7-12 |
| 34 | EE | Achim Nohl,
Volker Greive,
Gunnar Braun,
Andreas Hoffmann,
Rainer Leupers,
Oliver Schliebusch,
Heinrich Meyr:
Instruction encoding synthesis for architecture exploration using hierarchical processor models.
DAC 2003: 262-267 |
| 33 | EE | Gunnar Braun,
Andreas Wieferink,
Oliver Schliebusch,
Rainer Leupers,
Heinrich Meyr,
Achim Nohl:
Processor/Memory Co-Exploration on Multiple Abstraction Levels.
DATE 2003: 10966-10973 |
| 32 | EE | Oliver Wahlen,
Manuel Hohenauer,
Gunnar Braun,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Xiaoning Nie:
Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.
SCOPES 2003: 167-181 |
| 31 | EE | Desiree Ottoni,
Guilherme Ottoni,
Guido Araujo,
Rainer Leupers:
Improving Offset Assignment through Simultaneous Variable Coalescing.
SCOPES 2003: 285-297 |
| 30 | EE | Oliver Wahlen,
Manuel Hohenauer,
Rainer Leupers,
Heinrich Meyr:
Instruction Scheduler Generation for Retargetable Compilation.
IEEE Design & Test of Computers 20(1): 34-41 (2003) |
| 2002 |
|---|
| 29 | EE | Achim Nohl,
Gunnar Braun,
Oliver Schliebusch,
Rainer Leupers,
Heinrich Meyr,
Andreas Hoffmann:
A universal technique for fast and flexible instruction-set architecture simulation.
DAC 2002: 22-27 |
| 28 | EE | Oliver Wahlen,
Tilman Glökler,
Achim Nohl,
Andreas Hoffmann,
Rainer Leupers,
Heinrich Meyr:
Application specific compiler/architecture codesign: a case study.
LCTES-SCOPES 2002: 185-193 |
| 27 | EE | Rainer Leupers:
Compiler Design Issues for Embedded Processors.
IEEE Design & Test of Computers 19(4): 51-58 (2002) |
| 2001 |
|---|
| 26 | EE | Markus Lorenz,
David Koffmann,
Steven Bashford,
Rainer Leupers,
Peter Marwedel:
Optimized address assignment for DSPs with SIMD memory accesses.
ASP-DAC 2001: 415-420 |
| 25 | | Markus Lorenz,
Rainer Leupers,
Peter Marwedel,
Thorsten Dräger,
Gerhard Fettweis:
Low-Energy DSP Code Generation Using a Genetic Algorithm.
ICCD 2001: 431-437 |
| 24 | | Jens Wagner,
Rainer Leupers:
C Compiler Design for an Industrial Network Processor.
LCTES/OM 2001: 155-164 |
| 23 | EE | Jens Wagner,
Rainer Leupers:
C compiler design for a network processor.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1302-1308 (2001) |
| 2000 |
|---|
| 22 | EE | Rainer Leupers:
Register allocation for common subexpressions in DSP data paths.
ASP-DAC 2000: 235-240 |
| 21 | EE | Rainer Leupers:
Code Selection for Media Processors with SIMD Instructions.
DATE 2000: 4-8 |
| 20 | EE | Rainer Leupers:
Instruction Scheduling for Clustered VLIW DSPs.
IEEE PACT 2000: 291-300 |
| 19 | EE | Rainer Leupers:
Code Generation for Embedded Processors.
ISSS 2000: 173-179 |
| 18 | EE | Rainer Leupers,
Steven Bashford:
Graph-based code selection techniques for embedded processors.
ACM Trans. Design Autom. Electr. Syst. 5(4): 794-814 (2000) |
| 1999 |
|---|
| 17 | EE | Rainer Leupers,
Johann Elste,
Birger Landwehr:
Generation of Interpretive and Compiled Instruction Set Simulators.
ASP-DAC 1999: 339-342 |
| 16 | EE | Steven Bashford,
Rainer Leupers:
Constraint Driven Code Selection for Fixed-Point DSPs.
DAC 1999: 817-822 |
| 15 | EE | Rainer Leupers:
Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors.
DATE 1999: 105- |
| 14 | EE | Rainer Leupers,
Peter Marwedel:
Function inlining under code size constraints for embedded processors.
ICCAD 1999: 253-256 |
| 13 | | Anupam Basu,
Rainer Leupers,
Peter Marwedel:
Array Index Allocation under Register Constraints in DSP Programs.
VLSI Design 1999: 330-335 |
| 1998 |
|---|
| 12 | | Rainer Leupers,
Anupam Basu,
Peter Marwedel:
Optimized Array Index Computation in DSP Programs.
ASP-DAC 1998: 87-92 |
| 11 | EE | Anupam Basu,
Rainer Leupers,
Peter Marwedel:
Register-Constrained Address Computation in DSP Programs.
DATE 1998: 929-930 |
| 10 | EE | Rainer Leupers,
Fabian David:
A Uniform Optimization Technique for Offset Assignment Problems.
ISSS 1998: 3-8 |
| 9 | EE | Rainer Leupers:
HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation.
ISSS 1998: 51- |
| 1997 |
|---|
| 8 | EE | Rainer Leupers,
Peter Marwedel:
Retargetable generation of code selectors from HDL processor models.
ED&TC 1997: 140-144 |
| 7 | EE | Rainer Leupers,
Peter Marwedel:
Time-constrained code compaction for DSPs.
IEEE Trans. VLSI Syst. 5(1): 112-122 (1997) |
| 1996 |
|---|
| 6 | EE | Rainer Leupers,
Peter Marwedel:
Algorithms for address assignment in DSP code generation.
ICCAD 1996: 109-112 |
| 5 | | Rainer Leupers,
Peter Marwedel:
Instruction-Set Modeling for ASIP Code Generation.
VLSI Design 1996: 77-80 |
| 1995 |
|---|
| 4 | EE | Rainer Leupers,
Peter Marwedel:
Time-constrained code compaction for DSPs.
ISSS 1995: 54-59 |
| 1994 |
|---|
| 3 | EE | Peter Marwedel,
Rainer Leupers:
Instruction set extraction from programmable structures.
EURO-DAC 1994: 156-161 |
| 2 | | Rainer Leupers,
Wolfgang Schenk,
Peter Marwedel:
Microcode Generation for Flexible Parallel Target Architectures.
IFIP PACT 1994: 247-256 |
| 1993 |
|---|
| 1 | EE | Lorenz Ladage,
Rainer Leupers:
Resistance Extraction using a Routing Algorithm.
DAC 1993: 38-42 |
