| 2008 |
|---|
| 49 | EE | Chua-Chin Wang,
Chi-Chun Huang,
Jun-Han Wu,
I-Yu Huang:
A mini-invasive multi-function bladder urine pressure measurement system.
ISCAS 2008: 3174-3177 |
| 48 | EE | Gang-Neng Sung,
Yan-Jhin Ciou,
Chua-Chin Wang:
A power-aware 2-dimensional bypassing multiplier using cell-based design flow.
ISCAS 2008: 3338-3341 |
| 47 | EE | Tung-Han Tsai,
Chin-Lin Chen,
Ching-Li Lee,
Chua-Chin Wang:
Power-saving nano-scale DRAMs with an adaptive refreshing clock generator.
ISCAS 2008: 612-615 |
| 46 | EE | Chua-Chin Wang,
Chi-Chun Huang,
Ching-Li Lee,
Tsai-Wen Cheng:
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.
IEEE Trans. VLSI Syst. 16(5): 594-598 (2008) |
| 45 | EE | Chua-Chin Wang,
Chi-Chun Huang,
Jian-Ming Huang,
Chih-Yi Chang,
Chih-Peng Li:
ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network.
IEEE Trans. VLSI Syst. 16(7): 936-939 (2008) |
| 44 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Chi-Chun Huang,
Ching-Li Lee,
Tian-Hau Chen,
Wun-Ji Lin,
Ron Hu:
A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors.
Journal of Circuits, Systems, and Computers 17(5): 943-956 (2008) |
| 43 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Pai-Li Liu:
Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection.
Signal Processing Systems 52(2): 127-135 (2008) |
| 2007 |
|---|
| 42 | EE | Chua-Chin Wang,
Chi-Chun Huang,
Jian-Sing Liou,
Yan-Jhin Ciou,
I-Yu Huang,
Chih-Peng Li,
Yun-Chin Lee,
Wen-Jen Wu:
An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation Amplifier.
ISCAS 2007: 2383-2386 |
| 41 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Kuan-Wen Fang,
Sheng-Lun Tseng:
A Low-power Sensorless Inverter Controller of Brushless DC Motors.
ISCAS 2007: 2435-2438 |
| 40 | EE | Chua-Chin Wang,
Tzung-Je Lee,
Chih-Chen Li,
Ron Hu:
Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator.
Microelectronics Journal 38(2): 197-202 (2007) |
| 39 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Jian-Ming Huang,
Li-Pin Lin:
An 80MHz PLL with 72.7ps peak-to-peak jitter.
Microelectronics Journal 38(6-7): 716-721 (2007) |
| 2006 |
|---|
| 38 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Ming-Kai Chang,
Ching-Li Lee,
Cheng-Mu Wu,
Ju-Ya Chen:
A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers.
APCCAS 2006: 1112-1115 |
| 37 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Ming-Kai Chang,
Ying-Yu Shen:
Engery-Efficient Double-Edge Triggered Flip-Flop Design.
APCCAS 2006: 1791-1794 |
| 36 | EE | Chua-Chin Wang,
Tzung-Je Lee,
Chih-Chen Li,
Ron Hu:
An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity.
APCCAS 2006: 267-270 |
| 35 | EE | Chua-Chin Wang,
Chi-Chun Huang,
Tzung-Je Lee,
Cheng-Mu Wu,
Gang-Neng Sung,
Kuan-Wen Fang,
Sheng-Lun Tseng,
Jia-Jin Chen:
An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording.
APCCAS 2006: 682-685 |
| 34 | EE | Chua-Chin Wang,
Chi-Chun Huang,
Jian-Sing Liou,
Kuan-Wen Fang:
A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing.
APCCAS 2006: 696-699 |
| 33 | EE | Chua-Chin Wang,
Chi-Chun Huang,
Tzung-Je Lee,
U. Fat Chio:
A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR.
APCCAS 2006: 880-883 |
| 32 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Jia-Hao Li:
Codec Design for Variable-Length to Fixed-Length Data Conversion for H.263.
IIH-MSP 2006: 483-486 |
| 31 | EE | Chua-Chin Wang,
Ching-Li Lee,
Wun-Ji Lin:
A 4-Kb low power 4-T SRAM design with negative word-line gate drive.
ISCAS 2006 |
| 30 | EE | Chua-Chin Wang,
Jian-Ming Huang,
Chih-Yi Chang,
Kuang-Ting Cheng,
Chih-Peng Li:
A 6.57 mW ZigBee transceiver for 868/915 MHz band.
ISCAS 2006 |
| 29 | EE | Chua-Chin Wang,
Gang-Neng Sung:
A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology.
ISVLSI 2006: 405-410 |
| 2005 |
|---|
| 28 | EE | Chua-Chin Wang,
Ching-Li Lee,
Li-Ping Lin,
Yih-Long Tseng:
Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC.
ISCAS (1) 2005: 356-359 |
| 27 | EE | Chua-Chin Wang,
Tzung-Je Lee,
Yu-Tzu Hsiao,
U. Fat Chio,
Chi-Chun Huang,
J.-J. J. Chin,
Ya-Hsin Hsueh:
A multiparameter implantable microstimulator SOC.
IEEE Trans. VLSI Syst. 13(12): 1399-1402 (2005) |
| 26 | EE | Chua-Chin Wang,
Yih-Long Tseng,
Chih-Chiang Chiu:
A temperature-insensitive self-recharging circuitry used in DRAMs.
IEEE Trans. VLSI Syst. 13(3): 405-408 (2005) |
| 2004 |
|---|
| 25 | | Chua-Chin Wang,
Yih-Long Tseng,
Tzung-Je Lee,
Ron Hu:
High-PSR bias circuitry for NTSC sync separation.
ISCAS (1) 2004: 329-332 |
| 24 | | Chua-Chin Wang,
Ya-Hsin Hsueh,
Sen-Fu Hong,
Rong-Sui Kao:
A phase-adjustable negative phase shifter using a single-shot locking method.
ISCAS (2) 2004: 933-936 |
| 23 | | Chua-Chin Wang,
Ya-Hsin Hsueh,
U. Fat Chio,
Yu-Tzu Hsiao:
A C-less ASK demodulator for implantable neural interfacing chips.
ISCAS (4) 2004: 57-60 |
| 22 | EE | Chua-Chin Wang,
Yih-Long Tseng,
Hsien-Chih She,
Ron Hu:
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications.
IEEE Trans. VLSI Syst. 12(12): 1377-1381 (2004) |
| 21 | EE | Chua-Chin Wang,
Yih-Long Tseng,
Hsien-Chih She,
Chih-Chen Li,
Ron Hu:
A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula.
IEEE Trans. VLSI Syst. 12(9): 895-900 (2004) |
| 20 | EE | Chua-Chin Wang,
Yih-Long Tseng,
Hon-Yuan Leo,
Ron Hu:
A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.
IEEE Trans. VLSI Syst. 12(9): 901-909 (2004) |
| 2003 |
|---|
| 19 | EE | Chua-Chin Wang,
Ya-Hsin Hsueh,
Ying-Pei Chen:
An area-saving decoder structure for ROMs.
IEEE Trans. VLSI Syst. 11(4): 581-589 (2003) |
| 18 | EE | Chua-Chin Wang,
Po-Ming Lee,
Jun-Jie Wang,
Chenn-Jung Huang:
Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm.
IEEE Trans. VLSI Syst. 11(4): 737-740 (2003) |
| 2002 |
|---|
| 17 | EE | Chenn-Jung Huang,
Chua-Chin Wang,
Chi-Feng Wu:
Image Processing Techniques for Wafer Defect Cluster Identification.
IEEE Design & Test of Computers 19(2): 44-48 (2002) |
| 2001 |
|---|
| 16 | EE | Chua-Chin Wang,
Po-Ming Lee,
Rong-Chin Lee,
Chenn-Jung Huang:
A 1.25 GHz 32-bit tree-structured carry lookahead adder.
ISCAS (4) 2001: 80-83 |
| 15 | | Chenn-Jung Huang,
Wei Kuang Lai,
Chua-Chin Wang,
Yu-Jyr Jin,
Hsin Wei Chen:
A ratioed channel assignment scheme for initial and handoff calls in mobile cellular systems.
Computer Communications 24(3-4): 308-318 (2001) |
| 14 | EE | Chua-Chin Wang,
Cheng-Fa Tsai,
Yu-Tsun Chien:
Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network.
J. Inf. Sci. Eng. 17(2): 313-324 (2001) |
| 2000 |
|---|
| 13 | EE | Chua-Chin Wang,
Cheng-Fa Tsai:
A Novel Neural Architecture with High Storage Capacity.
IJCNN (5) 2000: 617-621 |
| 12 | | Chua-Chin Wang,
Chenn-Jung Huang,
Shiou-Ming Hwang:
A deterministic capacity-finding method for multi-valued exponential BAM.
IEEE Transactions on Systems, Man, and Cybernetics, Part A 30(6): 817-819 (2000) |
| 11 | | Chua-Chin Wang,
Cheng-Fa Tsai:
Fuzzy data processing using polynomial bidirectional hetero-associative network.
Inf. Sci. 125(1-4): 167-179 (2000) |
| 1999 |
|---|
| 10 | EE | Chua-Chin Wang,
Yu-Tsun Chien,
Ying-Pei Chen:
A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop.
ISCAS (2) 1999: 528-531 |
| 9 | EE | Chua-Chin Wang,
Cheng-Fa Tsai:
Theoretical expectation value of the capacity of fuzzy polynomial bidirectional hetero-correlator.
ISCAS (5) 1999: 583-586 |
| 1998 |
|---|
| 8 | | Chua-Chin Wang,
Chang-Rong Tsai:
Data compression by the recursive algorithm of exponential bidirectional associative memory.
IEEE Transactions on Systems, Man, and Cybernetics, Part B 28(2): 125-134 (1998) |
| 7 | | Chua-Chin Wang,
Hon-Son Don:
The Majority Theorem of Centralized Multiple BAMs Networks.
Inf. Sci. 110(3-4): 179-193 (1998) |
| 1997 |
|---|
| 6 | EE | Chua-Chin Wang,
Chih-Lwan Fan:
Digital Design of Discrete Exponential Bidirectional Associative Memory.
VLSI Signal Processing 15(3): 247-257 (1997) |
| 1996 |
|---|
| 5 | EE | Chua-Chin Wang:
Practical Capacity and Attraction Radix Analysis of Exponential Bidirectional Associative Memory.
J. Inf. Sci. Eng. 12(4): 511-523 (1996) |
| 1995 |
|---|
| 4 | | Chua-Chin Wang,
Jeng-Ming Wu:
Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory.
ISCAS 1995: 421-424 |
| 1994 |
|---|
| 3 | | Chua-Chin Wang,
Hon-Son Don:
A Polar Model for Evidential Reasoning.
Inf. Sci. 77(3-4): 195-226 (1994) |
| 2 | | Chua-Chin Wang,
Hon-Son Don:
A Modified Measure for Fuzzy Subsethood.
Inf. Sci. 79(3-4): 223-232 (1994) |
| 1 | EE | Chua-Chin Wang,
Hon-Son Don:
A robust continuous model for evidential reasoning.
Journal of Intelligent and Robotic Systems 10(2): 147-171 (1994) |
