2008 | ||
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1 | EE | Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng: A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. IEEE Trans. VLSI Syst. 16(5): 594-598 (2008) |
1 | Chi-Chun Huang | [1] |
2 | Ching-Li Lee | [1] |
3 | Chua-Chin Wang | [1] |