dblp.uni-trier.dewww.uni-trier.de

Tsai-Wen Cheng

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
1EEChua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng: A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. IEEE Trans. VLSI Syst. 16(5): 594-598 (2008)

Coauthor Index

1Chi-Chun Huang [1]
2Ching-Li Lee [1]
3Chua-Chin Wang [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)