| 2008 |
|---|
| 8 | EE | David L. Andrews,
Ron Sass,
Erik Anderson,
Jason Agron,
Wesley Peck,
Jim Stevens,
Fabrice Baijot,
Ed Komp:
Achieving Programming Model Abstractions for Reconfigurable Computing.
IEEE Trans. VLSI Syst. 16(1): 34-44 (2008) |
| 2007 |
|---|
| 7 | | Erik Anderson,
Wesley Peck,
Jim Stevens,
Jason Agron,
Fabrice Baijot,
Seth Warn,
David L. Andrews:
Memory Hierarchy for MCSoPC Multithreaded Systems.
ERSA 2007: 44-50 |
| 6 | EE | Jim Stevens:
Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C.
FPL 2007: 511-512 |
| 5 | EE | Erik Anderson,
Wesley Peck,
Jim Stevens,
Jason Agron,
Fabrice Baijot,
Seth Warn,
David L. Andrews:
Supporting High Level Language Semantics Within Hardware Resident Threads.
FPL 2007: 98-103 |
| 2006 |
|---|
| 4 | | David L. Andrews,
Ron Sass,
Erik Anderson,
Jason Agron,
Wesley Peck,
Jim Stevens,
Fabrice Baijot,
Ed Komp:
The Case for High Level Programming Models for Reconfigurable Computers.
ERSA 2006: 21-32 |
| 3 | EE | Erik Anderson,
Jason Agron,
Wesley Peck,
Jim Stevens,
Fabrice Baijot,
Ed Komp,
Ron Sass,
David L. Andrews:
Enabling a Uniform Programming Model Across the Software/Hardware Boundary.
FCCM 2006: 89-98 |
| 2 | EE | Wesley Peck,
Erik Anderson,
Jason Agron,
Jim Stevens,
Fabrice Baijot,
David L. Andrews:
Hthreads: A Computational Model for Reconfigurable Devices.
FPL 2006: 1-4 |
| 1 | EE | Jason Agron,
Wesley Peck,
Erik Anderson,
David L. Andrews,
Ed Komp,
Ron Sass,
Fabrice Baijot,
Jim Stevens:
Run-Time Services for Hybrid CPU/FPGA Systems on Chip.
RTSS 2006: 3-12 |
