N. Ranganathan

Nagarajan Ranganathan

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2009

140 EE Koustav Bhattacharya, Nagarajan Ranganathan: A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. ISQED 2009: 388-393

139 EE Koustav Bhattacharya, Nagarajan Ranganathan: RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. VLSI Design 2009: 453-458

138 EE Himanshu Thapliyal, Nagarajan Ranganathan: Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. VLSI Design 2009: 511-516

2008

137 EE N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam: Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. ACM Great Lakes Symposium on VLSI 2008: 171-176

136 EE Koustav Bhattacharya, Nagarajan Ranganathan: A linear programming formulation for security-aware gate sizing. ACM Great Lakes Symposium on VLSI 2008: 273-278

135 EE Upavan Gupta, Nagarajan Ranganathan: A microeconomic approach to multi-objective spatial clustering. ICPR 2008: 1-4

134 EE Upavan Gupta, Nagarajan Ranganathan: An expected-utility based approach to variation aware VLSI optimization under scarce information. ISLPED 2008: 81-86

133 EE Koustav Bhattacharya, Nagarajan Ranganathan: Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. ISLPED 2008: 99-104

132 EE Venkataraman Mahalingam, Nagarajan Ranganathan: A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. ISVLSI 2008: 329-334

131 EE Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow: A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. IEEE Trans. VLSI Syst. 16(8): 975-984 (2008)

2007

130 EE Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan: Improving the reliability of on-chip L2 cache using redundancy. ICCD 2007: 224-229

129 EE Upavan Gupta, Nagarajan Ranganathan: A microeconomic approach to multi-robot team formation. IROS 2007: 3019-3024

128 EE Venkataraman Mahalingam, N. Ranganathan: Variation Aware Timing Based Placement Using Fuzzy Programming. ISQED 2007: 327-332

127 EE Narender Hanchate, Nagarajan Ranganathan: Integrated Gate and Wire Sizing at Post Layout Level. ISVLSI 2007: 225-232

126 EE Narender Hanchate, Nagarajan Ranganathan: Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ISVLSI 2007: 245-252

125 EE Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan: A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. VLSI Design 2007: 215-220

124 EE Upavan Gupta, Nagarajan Ranganathan: Multievent Crisis Management Using Noncooperative Multistep Games. IEEE Trans. Computers 56(5): 577-589 (2007)

2006

123 EE Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III: A novel approach for variation aware power minimization during gate sizing. ISLPED 2006: 174-179

122 EE Narender Hanchate, Nagarajan Ranganathan: Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. ISQED 2006: 92-97

121 EE Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate: CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. ISVLSI 2006: 329-334

120 EE Narender Hanchate, Nagarajan Ranganathan: A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. VLSI Design 2006: 283-290

119 EE Venkataraman Mahalingam, N. Ranganathan: An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. VLSI Design 2006: 393-398

118 EE Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh: An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. VLSI Design 2006: 477-480

117 EE Aswath Oruganti, Nagarajan Ranganathan: Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. VLSI Design 2006: 766-769

116 EE Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: ILP models for simultaneous energy and transient power minimization during behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 11(1): 186-212 (2006)

115 EE Narender Hanchate, Nagarajan Ranganathan: A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ACM Trans. Design Autom. Electr. Syst. 11(3): 711-739 (2006)

114 EE Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan: A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11(3): 773-796 (2006)

113 EE Venkataraman Mahalingam, Nagarajan Ranganathan: Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. IEEE Trans. Computers 55(12): 1523-1535 (2006)

112 EE Narender Hanchate, Nagarajan Ranganathan: Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. IEEE Trans. Computers 55(8): 1011-1023 (2006)

2005

111 EE Venkataraman Mahalingam, N. Ranganathan: A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. ISVLSI 2005: 180-185

110 EE Saraju P. Mohanty, N. Ranganathan, K. Balakrishnan: Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. VLSI Design 2005: 153-158

109 EE Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan: Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design 2005: 586-591

108 EE Saraju P. Mohanty, N. Ranganathan: Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. ACM Trans. Design Autom. Electr. Syst. 10(2): 330-353 (2005)

107 EE Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design. IEEE Trans. VLSI Syst. 13(7): 808-818 (2005)

106 EE Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*. IEEE Trans. VLSI Syst. 13(8): 1002-1012 (2005)

2004

105 EE Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui: Control and Data Flow Graph Extraction for High-Level Synthesis. ISVLSI 2004: 192

104 EE Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. VLSI Design 2004: 1063-

103 EE Ashok K. Murugavel, N. Ranganathan: Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. VLSI Design 2004: 195-200

102 EE Narender Hanchate, Nagarajan Ranganathan: A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. VLSI Design 2004: 228-233

101 EE Ashok K. Murugavel, N. Ranganathan: Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. VLSI Design 2004: 670-

100 EE Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi: ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. VLSI Design 2004: 745-748

99 N. Ranganathan: Editorial. IEEE Trans. VLSI Syst. 12(1): 1-11 (2004)

98 EE Sanjukta Bhanja, N. Ranganathan: Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. VLSI Syst. 12(12): 1360-1370 (2004)

97 Narender Hanchate, Nagarajan Ranganathan: LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Trans. VLSI Syst. 12(2): 196-205 (2004)

96 EE Saraju P. Mohanty, Nagarajan Ranganathan: A framework for energy and transient power reduction during behavioral synthesis. IEEE Trans. VLSI Syst. 12(6): 562-572 (2004)

95 EE Ramamurti Chandramouli, Koduvayur P. Subbalakshmi, N. Ranganathan: Stochastic channel-adaptive rate control for wireless video transmission. Pattern Recognition Letters 25(7): 793-806 (2004)

2003

94 EE Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Simultaneous peak and average power minimization during datapath scheduling for DSP processors. ACM Great Lakes Symposium on VLSI 2003: 215-220

93 EE N. Ranganathan, Ashok K. Murugavel: A low power scheduler using game theory. CODES+ISSS 2003: 126-131

92 EE N. Ranganathan, Ashok K. Murugavel: A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. ICCD 2003: 276-281

91 EE Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. ICCD 2003: 441-443

90 EE Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. ISCAS (5) 2003: 313-316

89 EE Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Peak Power Minimization Through Datapath Scheduling. ISVLSI 2003: 121-126

88 EE Saraju P. Mohanty, N. Ranganathan: Energy Efficient Scheduling for Datapath Synthesis. VLSI Design 2003: 446-451

87 EE Ashok K. Murugavel, N. Ranganathan: A Game-Theoretic Approach for Binding in Behavioral Synthesis. VLSI Design 2003: 452-

86 EE Saraju P. Mohanty, N. Ranganathan: A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. VLSI Design 2003: 539-545

85 EE Abdel Ejnioui, N. Ranganathan: Multiterminal net routing for partial crossbar-based multi-FPGA systems. IEEE Trans. VLSI Syst. 11(1): 71-78 (2003)

84 EE Abdel Ejnioui, N. Ranganathan: Routing on field-programmable switch matrices. IEEE Trans. VLSI Syst. 11(2): 283-287 (2003)

83 EE Sanjukta Bhanja, N. Ranganathan: Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. VLSI Syst. 11(4): 558-567 (2003)

82 EE Ashok K. Murugavel, N. Ranganathan: Petri net modeling of gate and interconnect delays for power estimation. IEEE Trans. VLSI Syst. 11(5): 921-927 (2003)

81 EE Ashok K. Murugavel, N. Ranganathan: A game theoretic approach for power optimization during behavioral synthesis. IEEE Trans. VLSI Syst. 11(6): 1031-1043 (2003)

2002

80 EE K. Sitaraman, N. Ranganathan, Abdel Ejnioui: A VLSI Architecture for Object Recognition Using Tree Matching. ASAP 2002: 325-334

79 EE Ashok K. Murugavel, N. Ranganathan: Petri net modeling of gate and interconnect delays for power estimation. DAC 2002: 455-460

78 EE Sanjukta Bhanja, N. Ranganathan: Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. ICCD 2002: 388-390

77 EE Ashok K. Murugavel, N. Ranganathan: Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. ISLPED 2002: 267-270

76 EE Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna: Datapath Scheduling using Dynamic Frequency Clocking. ISVLSI 2002: 65-70

75 EE Ashok K. Murugavel, N. Ranganathan: A Real Delay Switching Activity Simulator Based on Petri Net Modeling. VLSI Design 2002: 181-186

74 EE Sanjukta Bhanja, N. Ranganathan: Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. VLSI Design 2002: 187-192

73 EE Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali: Least-square estimation of average power in digital CMOS circuits. IEEE Trans. VLSI Syst. 10(1): 55-58 (2002)

2001

72 EE Sanjukta Bhanja, N. Ranganathan: Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. DAC 2001: 209-214

71 EE Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali: Average Power in Digital CMOS Circuits using Least Square Estimation. VLSI Design 2001: 215-220

70 Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan: Context-based lossless image coding using EZW framework. IEEE Trans. Circuits Syst. Video Techn. 11(4): 554-559 (2001)

69 EE Abdel Ejnioui, N. Ranganathan: A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. IEEE Trans. VLSI Syst. 9(2): 407-410 (2001)

68 N. Ranganathan, Minesh I. Patel, R. Sathyamurthy: An intelligent system for failure detection and control in an autonomous underwater vehicle. IEEE Transactions on Systems, Man, and Cybernetics, Part A 31(6): 762-767 (2001)

2000

67 EE Raju D. Venkataramana, N. Ranganathan: New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems. Heterogeneous Computing Workshop 2000: 160-167

66 EE Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan: CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. VLSI Design 2000: 228-233

65 EE Abdel Ejnioui, N. Ranganathan: Design Partitioning on Single-Chip Emulation Systems. VLSI Design 2000: 234-239

64 EE Abdel Ejnioui, N. Ranganathan: Routing on Switch Matrix Multi-FPGA Systems. VLSI Design 2000: 248-253

63 EE Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan: VBR video traffic management using a predictor-based architecture. Computer Communications 23(1): 62-70 (2000)

1999

62 EE Narayanan Vijaykrishnan, N. Ranganathan: Tuning Branch Predictors to Support Virtual Method Invocation in Java. COOTS 1999: 217-228

61 EE Abdel Ejnioui, N. Ranganathan: Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. FPGA 1999: 176-185

60 EE Raju D. Venkataramana, N. Ranganathan: Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata. Heterogeneous Computing Workshop 1999: 137-145

59 EE Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan: Context based lossless intraframe coding of video sequence using embedded zerotree wavelets. ISCAS (4) 1999: 323-326

58 Hitoshi Oi, N. Ranganathan: Utilization of Cache Area in On-Chip Multiprocessor. ISHPC 1999: 373-380

57 EE Raju D. Venkataramana, N. Ranganathan: A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems. SAC 1999: 541-547

56 EE Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan: Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. VLSI Design 1999: 440-

55 EE Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan: Computation of lower bounds for switching activity using decision theory. IEEE Trans. VLSI Syst. 7(1): 125-129 (1999)

54 EE Vamsi Krishna, N. Ranganathan, Abdel Ejnioui: A tree-matching chip. IEEE Trans. VLSI Syst. 7(2): 277-280 (1999)

1998

53 EE Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss: Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission. Data Compression Conference 1998: 531

52 EE Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla: Object-Oriented Architectural Support for a Java Processor. ECOOP 1998: 330-354

51 EE Vamsi Krishna, N. Ranganathan: A Methodology for High Level Power Estimation and Exploration. Great Lakes Symposium on VLSI 1998: 420-425

50 Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan: Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission. ICIP (1) 1998: 649-653

49 Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan: Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. VLSI Design 1998: 230-233

48 Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu: A VLSI ATM Switch Architecture for VBR Traffic. VLSI Design 1998: 420-427

47 N. Ranganathan: A Forum for VLSI Practitioners. IEEE Computer 31(10): 86 (1998)

46 Raghu Sastry, N. Ranganathan: A VLSI Architecture for Approximate Tree Matching. IEEE Trans. Computers 47(3): 346-352 (1998)

45 EE N. Ranganathan, Raghu Sastry, R. Venkatesan: SMAC: A VLSI Architecture for Scene Matching. Real-Time Imaging 4(3): 171-180 (1998)

1997

44 Hitoshi Oi, N. Ranganathan: Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. ICCD 1997: 267-272

43 EE Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan: Performance Analysis of Wavelets in Embedded Zerotree-Based Lossless Image Coding Schemes. ICIP (2) 1997: 278-281

42 EE Ashley Rasquinha, N. Ranganathan: C3L: A Chip for Connected Component Labeling. VLSI Design 1997: 446-450

1996

41 EE Minesh I. Patel, N. Ranganathan: A VLSI System Architecture For Real-Time Intelligent Decision Making. ASAP 1996: 221-230

40 EE N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar: A VLSI array architecture with dynamic frequency clocking. ICCD 1996: 137-140

39 EE S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri: A VLSI chip for image compression using variable block size segmentation. ICCD 1996: 500-505

38 EE Vamsi Krishna, Abdel Ejnioui, N. Ranganathan: A tree matching chip. VLSI Design 1996: 280-285

37 EE Narayanan Vijaykrishnan, N. Ranganathan: SUBGEN: a genetic approach for subcircuit extraction. VLSI Design 1996: 343-345

1995

36 EE N. Ranganathan, K. B. Doreswamy: A systolic algorithm and architecture for image thinning. Great Lakes Symposium on VLSI 1995: 138-143

35 Raghu Sastry, N. Ranganathan: A VLSI Architecture for Computer the Tree-to-Tree Distance. HPCA 1995: 330-339

34 EE Abdel Ejnioui, N. Ranganathan: Systolic algorithms for tree pattern matching. ICCD 1995: 650-702

33 EE Mario Kovac, N. Ranganathan: JAGUAR: a high speed VLSI chip for JPEG image compression standard. VLSI Design 1995: 220-224

32 N. Ranganathan, Sharad C. Seth: Conference Reports. IEEE Design & Test of Computers 12(2): 5, 81 (1995)

31 EE Raghu Sastry, N. Ranganathan, Klinton Remedios: CASM: A VLSI Chip for Approximate String Matching. IEEE Trans. Pattern Anal. Mach. Intell. 17(8): 824-830 (1995)

30 EE Raghu Sastry, N. Ranganathan, Ramesh Jain: VLSI Architectures for High-Speed Range Estimation. IEEE Trans. Pattern Anal. Mach. Intell. 17(9): 894-899 (1995)

29 EE Nagarajan Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri: A lossless image compression algorithm using variable block size segmentation. IEEE Transactions on Image Processing 4(10): 1396-1406 (1995)

28 Raghu Sastry, N. Ranganathan: PMAC: A Polygon Matching Chip. IJPRAI 9(2): 367-385 (1995)

1994

27 N. Ranganathan, Satish Venugopal: A VLSI Chip for Template Matching. ICCD 1994: 542-545

26 N. Ranganathan, Satish Venugopal: An Efficient VLSI Architecture for Template Matching. ICPP (1) 1994: 224-231

25 N. Ranganathan, Bharadwaj Parthasarathy, Ken Hughes: A Parallel Algorithm and Architecture for Robot Path Planning. IPPS 1994: 275-279

24 Mario Kovac, N. Ranganathan: ACE: A VLSI Chip for Galois Field GF (2^m) Based Exponentiation. VLSI Design 1994: 291-296

23 N. Ranganathan, Raghu Sastry: VLSI Architectures for Pattern Matching. IJPRAI 8(4): 815-843 (1994)

22 Ken Hughes, N. Ranganathan: Modeling Sensor Confidence for Sensor Integration Tasks. IJPRAI 8(6): 1301-1318 (1994)

21 EE Kameswara Rao Namuduri, Rajiv Mehrotra, Nagarajan Ranganathan: Efficient computation of gabor filter based multiresolution responses. Pattern Recognition 27(7): 925-938 (1994)

1993

20 N. Ranganathan, Raghu Sastry, R. Venkatesan, Joseph W. Yoder, David C. Keezer: SMAC: A Scene Matching Chip. ICCD 1993: 184-187

19 Raghu Sastry, N. Ranganathan: A Systolic Array for Approximate String Matching. ICCD 1993: 402-405

18 Ken Hughes, N. Ranganathan: A Model for Determining Sensor Confidence. ICRA (2) 1993: 136-141

17 Raghu Sastry, N. Ranganathan, Ramesh Jain: VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. IPPS 1993: 700-704

16 Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: A VLSI Chip for Galois Field GF(2^m) Based Multiplication and Division. VLSI Design 1993: 25-30

15 Raghu Sastry, N. Ranganathan, Horst Bunke: Hardware Algorithms for Polygon Matching. VLSI Design 1993: 41-44

14 EE Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: a VLSI systolic array implementation of a Galois field GF(2 ^m) based multiplication and division algorithm. IEEE Trans. VLSI Syst. 1(1): 22-30 (1993)

13 EE Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, Tinku Acharya: MARVLE: a VLSI chip for data compression using tree-based codes. IEEE Trans. VLSI Syst. 1(2): 203-214 (1993)

12 EE Raghu Sastry, N. Ranganathan, Horst Bunke: VLSI architectures for polygon recognition. IEEE Trans. VLSI Syst. 1(4): 398-407 (1993)

1992

11 Amar Mukherjee, Jeffrey W. Flieder, N. Ranganathan: MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. ICCD 1992: 170-173

10 Mario Kovac, N. Ranganathan, M. Varanasi: A Systolic Algorithm and Architecture for Galois Field Arithmetic. IPPS 1992: 283-288

9 EE Rajiv Mehrotra, Kameswara Rao Namuduri, Nagarajan Ranganathan: Gabor filter-based edge detection. Pattern Recognition 25(12): 1479-1494 (1992)

1990

8 N. Ranganathan, Hassan N. Srinidhi: Effect of Data Compression Hardware on the Performance of a Relational Database Machine. PARBASE 1990: 144-146

7 EE S. Henriques, N. Ranganathan: A parallel architecture for data compression. SPDP 1990: 260-266

6 EE Rajiv Mehrotra, Sanjay Nichani, Nagarajan Ranganathan: Corner detection. Pattern Recognition 23(11): 1223-1233 (1990)

1989

5 EE Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan: On Software and Hardware Techniques of Data Engineering. ICDE 1989: 208-215

4 EE Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan: Enhancing arithmetic and tree-based coding. Inf. Process. Manage. 25(3): 293-305 (1989)

1988

3 EE Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee: A scheme for data compression in supercomputers. SC 1988: 272-278

2 EE Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee: Software and Hardware Enhancement of Arithmetic Coding. SSDBM 1988: 120-132

1 EE N. Ranganathan, Mubarak Shah: A VLSI architecture for computing scale space. Computer Vision, Graphics, and Image Processing 43(2): 178-204 (1988)

2009
140	EE	Koustav Bhattacharya, Nagarajan Ranganathan: A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. ISQED 2009: 388-393
139	EE	Koustav Bhattacharya, Nagarajan Ranganathan: RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. VLSI Design 2009: 453-458
138	EE	Himanshu Thapliyal, Nagarajan Ranganathan: Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. VLSI Design 2009: 511-516
2008
137	EE	N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam: Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. ACM Great Lakes Symposium on VLSI 2008: 171-176
136	EE	Koustav Bhattacharya, Nagarajan Ranganathan: A linear programming formulation for security-aware gate sizing. ACM Great Lakes Symposium on VLSI 2008: 273-278
135	EE	Upavan Gupta, Nagarajan Ranganathan: A microeconomic approach to multi-objective spatial clustering. ICPR 2008: 1-4
134	EE	Upavan Gupta, Nagarajan Ranganathan: An expected-utility based approach to variation aware VLSI optimization under scarce information. ISLPED 2008: 81-86
133	EE	Koustav Bhattacharya, Nagarajan Ranganathan: Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. ISLPED 2008: 99-104
132	EE	Venkataraman Mahalingam, Nagarajan Ranganathan: A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. ISVLSI 2008: 329-334
131	EE	Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow: A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. IEEE Trans. VLSI Syst. 16(8): 975-984 (2008)
2007
130	EE	Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan: Improving the reliability of on-chip L2 cache using redundancy. ICCD 2007: 224-229
129	EE	Upavan Gupta, Nagarajan Ranganathan: A microeconomic approach to multi-robot team formation. IROS 2007: 3019-3024
128	EE	Venkataraman Mahalingam, N. Ranganathan: Variation Aware Timing Based Placement Using Fuzzy Programming. ISQED 2007: 327-332
127	EE	Narender Hanchate, Nagarajan Ranganathan: Integrated Gate and Wire Sizing at Post Layout Level. ISVLSI 2007: 225-232
126	EE	Narender Hanchate, Nagarajan Ranganathan: Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ISVLSI 2007: 245-252
125	EE	Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan: A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. VLSI Design 2007: 215-220
124	EE	Upavan Gupta, Nagarajan Ranganathan: Multievent Crisis Management Using Noncooperative Multistep Games. IEEE Trans. Computers 56(5): 577-589 (2007)
2006
123	EE	Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III: A novel approach for variation aware power minimization during gate sizing. ISLPED 2006: 174-179
122	EE	Narender Hanchate, Nagarajan Ranganathan: Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. ISQED 2006: 92-97
121	EE	Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate: CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. ISVLSI 2006: 329-334
120	EE	Narender Hanchate, Nagarajan Ranganathan: A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. VLSI Design 2006: 283-290
119	EE	Venkataraman Mahalingam, N. Ranganathan: An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. VLSI Design 2006: 393-398
118	EE	Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh: An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. VLSI Design 2006: 477-480
117	EE	Aswath Oruganti, Nagarajan Ranganathan: Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. VLSI Design 2006: 766-769
116	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: ILP models for simultaneous energy and transient power minimization during behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 11(1): 186-212 (2006)
115	EE	Narender Hanchate, Nagarajan Ranganathan: A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ACM Trans. Design Autom. Electr. Syst. 11(3): 711-739 (2006)
114	EE	Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan: A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11(3): 773-796 (2006)
113	EE	Venkataraman Mahalingam, Nagarajan Ranganathan: Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. IEEE Trans. Computers 55(12): 1523-1535 (2006)
112	EE	Narender Hanchate, Nagarajan Ranganathan: Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. IEEE Trans. Computers 55(8): 1011-1023 (2006)
2005
111	EE	Venkataraman Mahalingam, N. Ranganathan: A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. ISVLSI 2005: 180-185
110	EE	Saraju P. Mohanty, N. Ranganathan, K. Balakrishnan: Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. VLSI Design 2005: 153-158
109	EE	Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan: Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design 2005: 586-591
108	EE	Saraju P. Mohanty, N. Ranganathan: Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. ACM Trans. Design Autom. Electr. Syst. 10(2): 330-353 (2005)
107	EE	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design. IEEE Trans. VLSI Syst. 13(7): 808-818 (2005)
106	EE	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*. IEEE Trans. VLSI Syst. 13(8): 1002-1012 (2005)
2004
105	EE	Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui: Control and Data Flow Graph Extraction for High-Level Synthesis. ISVLSI 2004: 192
104	EE	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. VLSI Design 2004: 1063-
103	EE	Ashok K. Murugavel, N. Ranganathan: Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. VLSI Design 2004: 195-200
102	EE	Narender Hanchate, Nagarajan Ranganathan: A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. VLSI Design 2004: 228-233
101	EE	Ashok K. Murugavel, N. Ranganathan: Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. VLSI Design 2004: 670-
100	EE	Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi: ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. VLSI Design 2004: 745-748
99		N. Ranganathan: Editorial. IEEE Trans. VLSI Syst. 12(1): 1-11 (2004)
98	EE	Sanjukta Bhanja, N. Ranganathan: Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. VLSI Syst. 12(12): 1360-1370 (2004)
97		Narender Hanchate, Nagarajan Ranganathan: LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Trans. VLSI Syst. 12(2): 196-205 (2004)
96	EE	Saraju P. Mohanty, Nagarajan Ranganathan: A framework for energy and transient power reduction during behavioral synthesis. IEEE Trans. VLSI Syst. 12(6): 562-572 (2004)
95	EE	Ramamurti Chandramouli, Koduvayur P. Subbalakshmi, N. Ranganathan: Stochastic channel-adaptive rate control for wireless video transmission. Pattern Recognition Letters 25(7): 793-806 (2004)
2003
94	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Simultaneous peak and average power minimization during datapath scheduling for DSP processors. ACM Great Lakes Symposium on VLSI 2003: 215-220
93	EE	N. Ranganathan, Ashok K. Murugavel: A low power scheduler using game theory. CODES+ISSS 2003: 126-131
92	EE	N. Ranganathan, Ashok K. Murugavel: A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. ICCD 2003: 276-281
91	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. ICCD 2003: 441-443
90	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. ISCAS (5) 2003: 313-316
89	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Peak Power Minimization Through Datapath Scheduling. ISVLSI 2003: 121-126
88	EE	Saraju P. Mohanty, N. Ranganathan: Energy Efficient Scheduling for Datapath Synthesis. VLSI Design 2003: 446-451
87	EE	Ashok K. Murugavel, N. Ranganathan: A Game-Theoretic Approach for Binding in Behavioral Synthesis. VLSI Design 2003: 452-
86	EE	Saraju P. Mohanty, N. Ranganathan: A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. VLSI Design 2003: 539-545
85	EE	Abdel Ejnioui, N. Ranganathan: Multiterminal net routing for partial crossbar-based multi-FPGA systems. IEEE Trans. VLSI Syst. 11(1): 71-78 (2003)
84	EE	Abdel Ejnioui, N. Ranganathan: Routing on field-programmable switch matrices. IEEE Trans. VLSI Syst. 11(2): 283-287 (2003)
83	EE	Sanjukta Bhanja, N. Ranganathan: Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. VLSI Syst. 11(4): 558-567 (2003)
82	EE	Ashok K. Murugavel, N. Ranganathan: Petri net modeling of gate and interconnect delays for power estimation. IEEE Trans. VLSI Syst. 11(5): 921-927 (2003)
81	EE	Ashok K. Murugavel, N. Ranganathan: A game theoretic approach for power optimization during behavioral synthesis. IEEE Trans. VLSI Syst. 11(6): 1031-1043 (2003)
2002
80	EE	K. Sitaraman, N. Ranganathan, Abdel Ejnioui: A VLSI Architecture for Object Recognition Using Tree Matching. ASAP 2002: 325-334
79	EE	Ashok K. Murugavel, N. Ranganathan: Petri net modeling of gate and interconnect delays for power estimation. DAC 2002: 455-460
78	EE	Sanjukta Bhanja, N. Ranganathan: Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. ICCD 2002: 388-390
77	EE	Ashok K. Murugavel, N. Ranganathan: Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. ISLPED 2002: 267-270
76	EE	Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna: Datapath Scheduling using Dynamic Frequency Clocking. ISVLSI 2002: 65-70
75	EE	Ashok K. Murugavel, N. Ranganathan: A Real Delay Switching Activity Simulator Based on Petri Net Modeling. VLSI Design 2002: 181-186
74	EE	Sanjukta Bhanja, N. Ranganathan: Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. VLSI Design 2002: 187-192
73	EE	Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali: Least-square estimation of average power in digital CMOS circuits. IEEE Trans. VLSI Syst. 10(1): 55-58 (2002)
2001
72	EE	Sanjukta Bhanja, N. Ranganathan: Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. DAC 2001: 209-214
71	EE	Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali: Average Power in Digital CMOS Circuits using Least Square Estimation. VLSI Design 2001: 215-220
70		Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan: Context-based lossless image coding using EZW framework. IEEE Trans. Circuits Syst. Video Techn. 11(4): 554-559 (2001)
69	EE	Abdel Ejnioui, N. Ranganathan: A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. IEEE Trans. VLSI Syst. 9(2): 407-410 (2001)
68		N. Ranganathan, Minesh I. Patel, R. Sathyamurthy: An intelligent system for failure detection and control in an autonomous underwater vehicle. IEEE Transactions on Systems, Man, and Cybernetics, Part A 31(6): 762-767 (2001)
2000
67	EE	Raju D. Venkataramana, N. Ranganathan: New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems. Heterogeneous Computing Workshop 2000: 160-167
66	EE	Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan: CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. VLSI Design 2000: 228-233
65	EE	Abdel Ejnioui, N. Ranganathan: Design Partitioning on Single-Chip Emulation Systems. VLSI Design 2000: 234-239
64	EE	Abdel Ejnioui, N. Ranganathan: Routing on Switch Matrix Multi-FPGA Systems. VLSI Design 2000: 248-253
63	EE	Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan: VBR video traffic management using a predictor-based architecture. Computer Communications 23(1): 62-70 (2000)
1999
62	EE	Narayanan Vijaykrishnan, N. Ranganathan: Tuning Branch Predictors to Support Virtual Method Invocation in Java. COOTS 1999: 217-228
61	EE	Abdel Ejnioui, N. Ranganathan: Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. FPGA 1999: 176-185
60	EE	Raju D. Venkataramana, N. Ranganathan: Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata. Heterogeneous Computing Workshop 1999: 137-145
59	EE	Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan: Context based lossless intraframe coding of video sequence using embedded zerotree wavelets. ISCAS (4) 1999: 323-326
58		Hitoshi Oi, N. Ranganathan: Utilization of Cache Area in On-Chip Multiprocessor. ISHPC 1999: 373-380
57	EE	Raju D. Venkataramana, N. Ranganathan: A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems. SAC 1999: 541-547
56	EE	Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan: Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. VLSI Design 1999: 440-
55	EE	Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan: Computation of lower bounds for switching activity using decision theory. IEEE Trans. VLSI Syst. 7(1): 125-129 (1999)
54	EE	Vamsi Krishna, N. Ranganathan, Abdel Ejnioui: A tree-matching chip. IEEE Trans. VLSI Syst. 7(2): 277-280 (1999)
1998
53	EE	Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss: Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission. Data Compression Conference 1998: 531
52	EE	Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla: Object-Oriented Architectural Support for a Java Processor. ECOOP 1998: 330-354
51	EE	Vamsi Krishna, N. Ranganathan: A Methodology for High Level Power Estimation and Exploration. Great Lakes Symposium on VLSI 1998: 420-425
50		Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan: Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission. ICIP (1) 1998: 649-653
49		Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan: Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. VLSI Design 1998: 230-233
48		Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu: A VLSI ATM Switch Architecture for VBR Traffic. VLSI Design 1998: 420-427
47		N. Ranganathan: A Forum for VLSI Practitioners. IEEE Computer 31(10): 86 (1998)
46		Raghu Sastry, N. Ranganathan: A VLSI Architecture for Approximate Tree Matching. IEEE Trans. Computers 47(3): 346-352 (1998)
45	EE	N. Ranganathan, Raghu Sastry, R. Venkatesan: SMAC: A VLSI Architecture for Scene Matching. Real-Time Imaging 4(3): 171-180 (1998)
1997
44		Hitoshi Oi, N. Ranganathan: Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. ICCD 1997: 267-272
43	EE	Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan: Performance Analysis of Wavelets in Embedded Zerotree-Based Lossless Image Coding Schemes. ICIP (2) 1997: 278-281
42	EE	Ashley Rasquinha, N. Ranganathan: C3L: A Chip for Connected Component Labeling. VLSI Design 1997: 446-450
1996
41	EE	Minesh I. Patel, N. Ranganathan: A VLSI System Architecture For Real-Time Intelligent Decision Making. ASAP 1996: 221-230
40	EE	N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar: A VLSI array architecture with dynamic frequency clocking. ICCD 1996: 137-140
39	EE	S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri: A VLSI chip for image compression using variable block size segmentation. ICCD 1996: 500-505
38	EE	Vamsi Krishna, Abdel Ejnioui, N. Ranganathan: A tree matching chip. VLSI Design 1996: 280-285
37	EE	Narayanan Vijaykrishnan, N. Ranganathan: SUBGEN: a genetic approach for subcircuit extraction. VLSI Design 1996: 343-345
1995
36	EE	N. Ranganathan, K. B. Doreswamy: A systolic algorithm and architecture for image thinning. Great Lakes Symposium on VLSI 1995: 138-143
35		Raghu Sastry, N. Ranganathan: A VLSI Architecture for Computer the Tree-to-Tree Distance. HPCA 1995: 330-339
34	EE	Abdel Ejnioui, N. Ranganathan: Systolic algorithms for tree pattern matching. ICCD 1995: 650-702
33	EE	Mario Kovac, N. Ranganathan: JAGUAR: a high speed VLSI chip for JPEG image compression standard. VLSI Design 1995: 220-224
32		N. Ranganathan, Sharad C. Seth: Conference Reports. IEEE Design & Test of Computers 12(2): 5, 81 (1995)
31	EE	Raghu Sastry, N. Ranganathan, Klinton Remedios: CASM: A VLSI Chip for Approximate String Matching. IEEE Trans. Pattern Anal. Mach. Intell. 17(8): 824-830 (1995)
30	EE	Raghu Sastry, N. Ranganathan, Ramesh Jain: VLSI Architectures for High-Speed Range Estimation. IEEE Trans. Pattern Anal. Mach. Intell. 17(9): 894-899 (1995)
29	EE	Nagarajan Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri: A lossless image compression algorithm using variable block size segmentation. IEEE Transactions on Image Processing 4(10): 1396-1406 (1995)
28		Raghu Sastry, N. Ranganathan: PMAC: A Polygon Matching Chip. IJPRAI 9(2): 367-385 (1995)
1994
27		N. Ranganathan, Satish Venugopal: A VLSI Chip for Template Matching. ICCD 1994: 542-545
26		N. Ranganathan, Satish Venugopal: An Efficient VLSI Architecture for Template Matching. ICPP (1) 1994: 224-231
25		N. Ranganathan, Bharadwaj Parthasarathy, Ken Hughes: A Parallel Algorithm and Architecture for Robot Path Planning. IPPS 1994: 275-279
24		Mario Kovac, N. Ranganathan: ACE: A VLSI Chip for Galois Field GF (2^m) Based Exponentiation. VLSI Design 1994: 291-296
23		N. Ranganathan, Raghu Sastry: VLSI Architectures for Pattern Matching. IJPRAI 8(4): 815-843 (1994)
22		Ken Hughes, N. Ranganathan: Modeling Sensor Confidence for Sensor Integration Tasks. IJPRAI 8(6): 1301-1318 (1994)
21	EE	Kameswara Rao Namuduri, Rajiv Mehrotra, Nagarajan Ranganathan: Efficient computation of gabor filter based multiresolution responses. Pattern Recognition 27(7): 925-938 (1994)
1993
20		N. Ranganathan, Raghu Sastry, R. Venkatesan, Joseph W. Yoder, David C. Keezer: SMAC: A Scene Matching Chip. ICCD 1993: 184-187
19		Raghu Sastry, N. Ranganathan: A Systolic Array for Approximate String Matching. ICCD 1993: 402-405
18		Ken Hughes, N. Ranganathan: A Model for Determining Sensor Confidence. ICRA (2) 1993: 136-141
17		Raghu Sastry, N. Ranganathan, Ramesh Jain: VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. IPPS 1993: 700-704
16		Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: A VLSI Chip for Galois Field GF(2^m) Based Multiplication and Division. VLSI Design 1993: 25-30
15		Raghu Sastry, N. Ranganathan, Horst Bunke: Hardware Algorithms for Polygon Matching. VLSI Design 1993: 41-44
14	EE	Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: a VLSI systolic array implementation of a Galois field GF(2 ^m) based multiplication and division algorithm. IEEE Trans. VLSI Syst. 1(1): 22-30 (1993)
13	EE	Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, Tinku Acharya: MARVLE: a VLSI chip for data compression using tree-based codes. IEEE Trans. VLSI Syst. 1(2): 203-214 (1993)
12	EE	Raghu Sastry, N. Ranganathan, Horst Bunke: VLSI architectures for polygon recognition. IEEE Trans. VLSI Syst. 1(4): 398-407 (1993)
1992
11		Amar Mukherjee, Jeffrey W. Flieder, N. Ranganathan: MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. ICCD 1992: 170-173
10		Mario Kovac, N. Ranganathan, M. Varanasi: A Systolic Algorithm and Architecture for Galois Field Arithmetic. IPPS 1992: 283-288
9	EE	Rajiv Mehrotra, Kameswara Rao Namuduri, Nagarajan Ranganathan: Gabor filter-based edge detection. Pattern Recognition 25(12): 1479-1494 (1992)
1990
8		N. Ranganathan, Hassan N. Srinidhi: Effect of Data Compression Hardware on the Performance of a Relational Database Machine. PARBASE 1990: 144-146
7	EE	S. Henriques, N. Ranganathan: A parallel architecture for data compression. SPDP 1990: 260-266
6	EE	Rajiv Mehrotra, Sanjay Nichani, Nagarajan Ranganathan: Corner detection. Pattern Recognition 23(11): 1223-1233 (1990)
1989
5	EE	Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan: On Software and Hardware Techniques of Data Engineering. ICDE 1989: 208-215
4	EE	Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan: Enhancing arithmetic and tree-based coding. Inf. Process. Manage. 25(3): 293-305 (1989)
1988
3	EE	Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee: A scheme for data compression in supercomputers. SC 1988: 272-278
2	EE	Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee: Software and Hardware Enhancement of Arithmetic Coding. SSDBM 1988: 120-132
1	EE	N. Ranganathan, Mubarak Shah: A VLSI architecture for computing scale space. Computer Vision, Graphics, and Image Processing 43(2): 178-204 (1988)

Coauthor Index

1 Tinku Acharya [13]

2 Rajat Anand [48]

3 S. B. Aruru [39]

4 K. Balakrishnan [110]

5 Mostafa A. Bassiouni [2] [3] [4] [5]

6 Sanjukta Bhanja [72] [74] [78] [83] [98] [109] [114]

7 Koustav Bhattacharya [130] [133] [136] [139] [140]

8 N. Bhavanishankar [40]

9 Horst Bunke [12] [15]

10 Ramamurti Chandramouli [49] [50] [53] [55] [71] [73] [95]

11 Sunil K. Chappidi [89] [90] [91] [94] [100] [116]

12 Srinath Chavali [71] [73]

13 Girish Chiruvolu [48] [63]

14 K. B. Doreswamy [36]

15 Abdel Ejnioui [34] [38] [54] [61] [64] [65] [69] [80] [84] [85] [105]

16 Jeffrey W. Flieder [11] [13]

17 Ravi Gadekarla [52]

18 Upavan Gupta [124] [129] [134] [135] [137]

19 Narender Hanchate [97] [102] [112] [115] [120] [121] [122] [126] [127]

20 J. E. Harlow [131]

21 Justin E. Harlow III [123]

22 S. Henriques [7]

23 Ken Hughes [18] [22] [25]

24 Ramesh Jain [17] [30]

25 Srinivas Katkoori [125]

26 David C. Keezer [20]

27 Soontae Kim [130]

28 Mario Kovac [10] [14] [16] [24] [33]

29 Vamsi Krishna [38] [49] [51] [54] [55] [56] [76]

30 Sharad Kumar [50]

31 Karthikeyan Lingasubramanian [109] [114]

32 Venkataraman Mahalingam [111] [113] [119] [123] [128] [131] [132] [137]

33 Rajiv Mehrotra [6] [9] [21]

34 Saraju P. Mohanty [76] [86] [88] [89] [90] [91] [94] [96] [100] [104] [106] [107] [108] [110] [116]

35 Amar Mukherjee [2] [3] [4] [5] [11] [13]

36 Ashok K. Murugavel [71] [73] [75] [77] [79] [81] [82] [87] [92] [93] [101] [103]

37 Ravi Namballa [104] [105] [106] [107] [121]

38 Kameswara Rao Namuduri [9] [21] [29] [39] [43] [59] [70]

39 Sanjay Nichani [6]

40 Hitoshi Oi [44] [58]

41 Aswath Oruganti [117]

42 Bharadwaj Parthasarathy [25]

43 Minesh I. Patel [41] [68]

44 Shivaraman J. Ramadoss [53]

45 Veeru N. Ramaswamy [43] [59] [70]

46 Ashley Rasquinha [42]

47 Klinton Remedios [31]

48 Steve G. Romaniuk [29]

49 Soumyaroop Roy [125]

50 Viswanath Sairaman [118]

51 Ravi Sankar [63]

52 Raghu Sastry [12] [15] [17] [19] [20] [23] [28] [30] [31] [35] [45] [46]

53 R. Sathyamurthy [68]

54 Sharad C. Seth [32]

55 Mubarak Shah [1]

56 Neeta S. Singh [118]

57 K. Sitaraman [80]

58 Vamsi K. Srikantam [66]

59 Hassan N. Srinidhi [8]

60 Srikanth Srinivasan [66]

61 K. P. Subbalakshmi (Koduvayur P. Subbalakshmi) [95]

62 Himanshu Thapliyal [138]

63 M. Varanasi [10] [14] [16]

64 Raju D. Venkataramana [57] [60] [67]

65 R. Venkatesan [20] [45]

66 Satish Venugopal [26] [27]

67 Narayanan Vijaykrishnan (Vijaykrishnan Narayanan) [37] [40] [52] [56] [62]

68 Joseph W. Yoder [20]

Colors in the list of coauthors

1	Tinku Acharya	[13]
2	Rajat Anand	[48]
3	S. B. Aruru	[39]
4	K. Balakrishnan	[110]
5	Mostafa A. Bassiouni	[2] [3] [4] [5]
6	Sanjukta Bhanja	[72] [74] [78] [83] [98] [109] [114]
7	Koustav Bhattacharya	[130] [133] [136] [139] [140]
8	N. Bhavanishankar	[40]
9	Horst Bunke	[12] [15]
10	Ramamurti Chandramouli	[49] [50] [53] [55] [71] [73] [95]
11	Sunil K. Chappidi	[89] [90] [91] [94] [100] [116]
12	Srinath Chavali	[71] [73]
13	Girish Chiruvolu	[48] [63]
14	K. B. Doreswamy	[36]
15	Abdel Ejnioui	[34] [38] [54] [61] [64] [65] [69] [80] [84] [85] [105]
16	Jeffrey W. Flieder	[11] [13]
17	Ravi Gadekarla	[52]
18	Upavan Gupta	[124] [129] [134] [135] [137]
19	Narender Hanchate	[97] [102] [112] [115] [120] [121] [122] [126] [127]
20	J. E. Harlow	[131]
21	Justin E. Harlow III	[123]
22	S. Henriques	[7]
23	Ken Hughes	[18] [22] [25]
24	Ramesh Jain	[17] [30]
25	Srinivas Katkoori	[125]
26	David C. Keezer	[20]
27	Soontae Kim	[130]
28	Mario Kovac	[10] [14] [16] [24] [33]
29	Vamsi Krishna	[38] [49] [51] [54] [55] [56] [76]
30	Sharad Kumar	[50]
31	Karthikeyan Lingasubramanian	[109] [114]
32	Venkataraman Mahalingam	[111] [113] [119] [123] [128] [131] [132] [137]
33	Rajiv Mehrotra	[6] [9] [21]
34	Saraju P. Mohanty	[76] [86] [88] [89] [90] [91] [94] [96] [100] [104] [106] [107] [108] [110] [116]
35	Amar Mukherjee	[2] [3] [4] [5] [11] [13]
36	Ashok K. Murugavel	[71] [73] [75] [77] [79] [81] [82] [87] [92] [93] [101] [103]
37	Ravi Namballa	[104] [105] [106] [107] [121]
38	Kameswara Rao Namuduri	[9] [21] [29] [39] [43] [59] [70]
39	Sanjay Nichani	[6]
40	Hitoshi Oi	[44] [58]
41	Aswath Oruganti	[117]
42	Bharadwaj Parthasarathy	[25]
43	Minesh I. Patel	[41] [68]
44	Shivaraman J. Ramadoss	[53]
45	Veeru N. Ramaswamy	[43] [59] [70]
46	Ashley Rasquinha	[42]
47	Klinton Remedios	[31]
48	Steve G. Romaniuk	[29]
49	Soumyaroop Roy	[125]
50	Viswanath Sairaman	[118]
51	Ravi Sankar	[63]
52	Raghu Sastry	[12] [15] [17] [19] [20] [23] [28] [30] [31] [35] [45] [46]
53	R. Sathyamurthy	[68]
54	Sharad C. Seth	[32]
55	Mubarak Shah	[1]
56	Neeta S. Singh	[118]
57	K. Sitaraman	[80]
58	Vamsi K. Srikantam	[66]
59	Hassan N. Srinidhi	[8]
60	Srikanth Srinivasan	[66]
61	K. P. Subbalakshmi (Koduvayur P. Subbalakshmi)	[95]
62	Himanshu Thapliyal	[138]
63	M. Varanasi	[10] [14] [16]
64	Raju D. Venkataramana	[57] [60] [67]
65	R. Venkatesan	[20] [45]
66	Satish Venugopal	[26] [27]
67	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[37] [40] [52] [56] [62]
68	Joseph W. Yoder	[20]