José G. Delgado-Frias

2009
50	EE	Ruirui Guo, José G. Delgado-Frias: IP Routing table compaction and sampling schemes to enhance TCAM cache performance. Journal of Systems Architecture - Embedded Systems Design 55(1): 61-69 (2009)
2008
49		Jason Van Dyken, José G. Delgado-Frias, Sirisha Medidi: FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. ERSA 2008: 311-312
48	EE	Michael A. Turi, José G. Delgado-Frias: High-performance low-power AND and Sense-Amp address decoders with selective precharging. ISCAS 2008: 1464-1467
47	EE	Mitchell J. Myjak, José G. Delgado-Frias: A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. IEEE Trans. VLSI Syst. 16(1): 14-23 (2008)
2007
46		H. Lui, José G. Delgado-Frias, Sirisha Medidi: Using a two-timer scheme to detect selfish nodes in mobile ad-hoc networks. Communications, Internet, and Information Technology 2007: 181-186
45		R. Guo, José G. Delgado-Frias: A novel compaction scheme for routing tables in TCAM to enhance cache hit rate. Communications, Internet, and Information Technology 2007: 210-215
44		H. Lin, José G. Delgado-Frias, Sirisha Medidi: Using a cache scheme to detect selfish nodes in mobile ad hoc networks. Communications, Internet, and Information Technology 2007: 61-66
43	EE	Rongsen He, José G. Delgado-Frias: Redundant Array of Independent Fabrics - An Architecture for Next Generation Network. GLOBECOM 2007: 2763-2768
42	EE	Li Zhao, José G. Delgado-Frias: MARS: Misbehavior Detection in Ad Hoc Networks. GLOBECOM 2007: 941-945
41	EE	Daniel R. Blum, José G. Delgado-Frias: Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. ISCAS 2007: 2786-2789
40	EE	Rongsen He, José G. Delgado-Frias: Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers. IEEE Trans. Parallel Distrib. Syst. 18(12): 1727-1739 (2007)
39	EE	Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru: Preface. Integration 40(2): 61 (2007)
2006
38	EE	Rongsen He, José G. Delgado-Frias: Interleaved Multistage Switching Fabrics for Scalable High Performance Routers. GLOBECOM 2006
37	EE	Suryanarayana Tatapudi, José G. Delgado-Frias: A mesochronous pipeline scheme for high performance low power digital systems. ISCAS 2006
36	EE	Mitchell J. Myjak, José G. Delgado-Frias: Superpipelined reconfigurable hardware for DSP. ISCAS 2006
35		Li Zhao, José G. Delgado-Frias: On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks. Wireless and Optical Communications 2006
2005
34		Laurence Tianruo Yang, Hamid R. Arabnia, Yiming Li, Salam N. Salloum, José G. Delgado-Frias: Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005 CSREA Press 2005
33		Mitchell J. Myjak, José G. Delgado-Frias: A Symmetric Differential Clock Generator for Bit-Serial Hardware. CDES 2005: 159-164
32		Suryanarayana Tatapudi, José G. Delgado-Frias: A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. CDES 2005: 191-197
31		Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias: Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. CDES 2005: 28-34
30		Jin Liu, José G. Delgado-Frias: DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. CDES 2005: 97-103
29	EE	Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias: A distributed FIFO scheme for on chip communication. ISCAS (2) 2005: 1851-1854
28	EE	Suryanarayana Tatapudi, José G. Delgado-Frias: A High Performance Hybrid Wave-Pipelined Multiplier. ISVLSI 2005: 282-283
2004
27		Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias: H-Tree Interconnection Structure for Reconfigurable DSP Hardware. ERSA 2004: 170-176
26		Andy Widjaja, José G. Delgado-Frias: An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware. ESA/VLSI 2004: 530-535
25		Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias: A Distributed FIFO Scheme for System on Chip Inter-Component Communication. ESA/VLSI 2004: 536-540
24	EE	Mitchell J. Myjak, José G. Delgado-Frias: Pipelined Multipliers for Reconfigurable Hardware. IPDPS 2004
2003
23		Mitchell J. Myjak, José G. Delgado-Frias: A Two-Level Reconfigurable Architecture for Digital Signal Processing. VLSI 2003: 21-27
22		Fred L. Anderson IV, José G. Delgado-Frias: A Reconfigurable Switch for a DSP Array. VLSI 2003: 3-6
21		Daniel R. Blum, José G. Delgado-Frias: A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. VLSI 2003: 58-64
2001
20	EE	José G. Delgado-Frias, Girish B. Ratanpal: A VLSI wrapped wave front arbiter for crossbar switches. ACM Great Lakes Symposium on VLSI 2001: 85-88
19	EE	Victor A. Skormin, José G. Delgado-Frias, Dennis L. McGee, Joseph Giordano, Leonard J. Popyack, Vladimir I. Gorodetski, Alexander O. Tarakanov: BASIS: A Biological Approach to System Information Security. MMM-ACNS 2001: 127-142
2000
18	EE	José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan: A wave-pipelined router architecture using ternary associative memory. ACM Great Lakes Symposium on VLSI 2000: 67-70
1998
17		Douglas H. Summerville, José G. Delgado-Frias: Approaches for determining dynamic synchronization resource requirements. Computers and Their Applications 1998: 385-388
16	EE	José G. Delgado-Frias, Richard Diaz: A VLSI Self-Compacting Buffer for DAMQ Communication Switches. Great Lakes Symposium on VLSI 1998: 128-133
15	EE	Adger E. Harvin III, José G. Delgado-Frias: A Dictionary Machine Emulation on a VLSI Computing Tree System. Great Lakes Symposium on VLSI 1998: 134-139
14	EE	José G. Delgado-Frias, Jabulani Nyathi: A VLSI High-Performance Encoder with Priority Lookahead. Great Lakes Symposium on VLSI 1998: 59-64
13	EE	Chien-Ying Lu, José G. Delgado-Frias, Wei Lin: A Clustering and Genetic Scheme for Large Tsp Optimization Problems. Cybernetics and Systems 29(2): 137-157 (1998)
1996
12		Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville: A Pattern-Associative Router for Interconnection Network Adaptive Algorithms. Euro-Par, Vol. I 1996: 213-217
11	EE	José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville: A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. Great Lakes Symposium on VLSI 1996: 246-251
10		Ming Zhang, Stamatis Vassiliadis, José G. Delgado-Frias: Sigmoid Generators for Neural Computing Using Piecewise Approximations. IEEE Trans. Computers 45(9): 1045-1049 (1996)
9	EE	Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis: A Flexible Bit-Pattern Associative Router for Interconnection Networks. IEEE Trans. Parallel Distrib. Syst. 7(5): 477-485 (1996)
1995
8		Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis: A Neuro-Architecture with Embedded Learning. Parallel and Distributed Computing and Systems 1995: 103-106
7		Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville: A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks. Parallel and Distributed Computing and Systems 1995: 238-242
6		Adger E. Harvin III, José G. Delgado-Frias: A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing. Parallel and Distributed Computing and Systems 1995: 455-458
5		Joonho Park, Stamatis Vassiliadis, José G. Delgado-Frias: Flexible oblivious router architecture. IBM Journal of Research and Development 39(3): 315-330 (1995)
1994
4		Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis: A High Performance Pattern Associative Oblivious Router for Tree Topologies. IPPS 1994: 541-545
3	EE	Joonho Park, Brian W. O'Krafka, Stamatis Vassiliadis, José G. Delgado-Frias: Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers. SC 1994: 713-722
1991
2		Robert H. Payne, José G. Delgado-Frias: MPU: A N-Tuple Matching Processor. ICCD 1991: 225-228
1988
1	EE	José G. Delgado-Frias, D. M. Green: BVE: a wafer-scale engine for differential equation computation. ICS 1988: 101-107

Coauthor Index

1	Valentine C. Aikens II	[8]
2	Fredrick L. Anderson	[27]
3	Fred L. Anderson IV	[22]
4	Hamid R. Arabnia	[34]
5	Steven M. Barber	[8]
6	Laxmi N. Bhuyan	[18]
7	Daniel R. Blum	[21] [31] [41]
8	Richard Diaz	[16]
9	Jason Van Dyken	[49]
10	Joseph Giordano	[19]
11	Vladimir I. Gorodetski	[19]
12	D. M. Green	[1]
13	R. Guo	[45]
14	Ruirui Guo	[50]
15	Adger E. Harvin III	[6] [15]
16	Rongsen He	[38] [40] [43]
17	Yiming Li	[34] [39]
18	H. Lin	[44]
19	Wei Lin	[13]
20	Jin Liu	[30]
21	Chien-Ying Lu	[13]
22	H. Lui	[46]
23	Dennis L. McGee	[19]
24	Sirisha Medidi	[44] [46] [49]
25	Chester L. Miller	[11]
26	Mitchell J. Myjak	[23] [24] [27] [31] [33] [36] [47]
27	Mohammed Y. Niamat	[39]
28	Jabulani Nyathi	[11] [14] [18] [25] [29]
29	Brian W. O'Krafka	[3]
30	Joonho Park	[3] [5]
31	Robert H. Payne	[2]
32	Gerald G. Pechanek	[8]
33	Leonard J. Popyack	[19]
34	Girish B. Ratanpal	[20]
35	Daniel G. Rice	[7] [12]
36	Ray Robert Rydberg III	[25] [29]
37	Salam N. Salloum	[34]
38	Victor A. Skormin	[19]
39	Dimitrios Soudris (D. J. Soudris)	[39]
40	Douglas H. Summerville	[4] [7] [9] [11] [12] [17]
41	Alexander O. Tarakanov	[19]
42	Suryanarayana Tatapudi	[28] [32] [37]
43	Michael A. Turi	[48]
44	Stamatis Vassiliadis	[3] [4] [5] [8] [9] [10]
45	Srinivasa Vemuru	[39]
46	Andy Widjaja	[26]
47	Laurence Tianruo Yang	[34] [39]
48	Ming Zhang	[10]
49	Li Zhao	[35] [42]

Colors in the list of coauthors