40. DAC 2003:
Anaheim,
CA,
USA
Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003.
ACM 2003, ISBN 1-58113-688-9 BibTeX
@proceedings{DBLP:conf/dac/2003,
title = {Proceedings of the 40th Design Automation Conference, DAC 2003,
Anaheim, CA, USA, June 2-6, 2003},
booktitle = {DAC},
publisher = {ACM},
year = {2003},
isbn = {1-58113-688-9},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Real challenges and solutions for validating system-on-chip
Reshaping EDA for power
Design for manufacturability and global routing
Design analysis techniques
- Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino:
Energy-aware design techniques for differential power analysis protection.
36-41
Electronic Edition (ACM DL) BibTeX
- Franco Fummi, Giovanni Perbellini, Paolo Gallo, Massimo Poncino, Stefano Martini, Fabio Ricciato:
A timing-accurate modeling and simulation environment for networked embedded systems.
42-47
Electronic Edition (ACM DL) BibTeX
- Robertas Damasevicius, Giedrius Majauskas, Vytautas Stuikys:
Application of design patterns for hardware design.
48-53
Electronic Edition (ACM DL) BibTeX
Embedded hardware design case studies
- George Kornaros, Ioannis Papaefstathiou, Aristides Nikologiannis, Nicholaos Zervos:
A fully-programmable memory management system optimizing queue handling at multi-gigabit rates.
54-59
Electronic Edition (ACM DL) BibTeX
- David Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazuo Sakiyama, Yi Fan, Shenglin Yang, Alireza Hodjat, Ingrid Verbauwhede:
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system.
60-65
Electronic Edition (ACM DL) BibTeX
- Jennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak:
Design techniques for sensor appliances: foundations and light compass case study.
66-71
Electronic Edition (ACM DL) BibTeX
Emerging design and tool challenges in RF and wireless applications
COT-customer owned trouble
- Robert Dahlberg, Shishpal Rawat, Jen Bernier, Gina Gloski, Aurangzeb Khan, Kaushik Patel, Paul Ruddy, Naveed A. Sherwani, Ronnie Vasishta:
COT - customer owned trouble.
91-92
Electronic Edition (ACM DL) BibTeX
- Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Random walks in a supply network.
93-98
Electronic Edition (ACM DL) BibTeX
- Dionysios Kouroussis, Farid N. Najm:
A static pattern-independent technique for power grid voltage integrity verification.
99-104
Electronic Edition (ACM DL) BibTeX
- Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng:
Power network analysis using an adaptive algebraic multigrid approach.
105-108
Electronic Edition (ACM DL) BibTeX
- Haihua Su, Emrah Acar, Sani R. Nassif:
Power grid reduction based on algebraic multigrid principles.
109-112
Electronic Edition (ACM DL) BibTeX
- Kai Wang, Malgorzata Marek-Sadowska:
On-chip power supply network optimization using multigrid-based technique.
113-118
Electronic Edition (ACM DL) BibTeX
Low-power embedded system design
Cyclic and non-cyclic combinational circuit synthesis
Managing leakage power
- Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy:
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.
169-174
Electronic Edition (ACM DL) BibTeX
- Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester:
Analysis and minimization techniques for total leakage considering gate oxide leakage.
175-180
Electronic Edition (ACM DL) BibTeX
- Changbo Long, Lei He:
Distributed sleep transistor network for power reduction.
181-186
Electronic Edition (ACM DL) BibTeX
- Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin:
Implications of technology scaling on leakage reduction techniques.
187-190
Electronic Edition (ACM DL) BibTeX
- Dongwoo Lee, David Blaauw:
Static leakage reduction through simultaneous threshold voltage and state assignment.
191-194
Electronic Edition (ACM DL) BibTeX
Emerging markets:
design goes global
- Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei:
Emerging markets: design goes global.
195
Electronic Edition (ACM DL) BibTeX
- Giancarlo Beraudo, John Lillis:
Timing optimization of FPGA placements by logic replication.
196-201
Electronic Edition (ACM DL) BibTeX
- Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Delay budgeting in sequential circuit with application on FPGA placement.
202-207
Electronic Edition (ACM DL) BibTeX
- Jason Cong, Xin Yuan:
Multilevel global placement with retiming.
208-213
Electronic Edition (ACM DL) BibTeX
- Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin:
Force directed mongrel with physical net constraints.
214-219
Electronic Edition (ACM DL) BibTeX
Model order reduction
Issues in partitioning & design space epolartion for codesign
- Radoslaw Szymanek, Krzysztof Kuchcinski:
Partial task assignment of task graphs under heterogeneous resource constraints.
244-249
Electronic Edition (ACM DL) BibTeX
- Greg Stitt, Roman L. Lysecky, Frank Vahid:
Dynamic hardware/software partitioning: a first approach.
250-255
Electronic Edition (ACM DL) BibTeX
- Kubilay Atasu, Laura Pozzi, Paolo Ienne:
Automatic application-specific instruction-set extensions under microarchitectural constraints.
256-261
Electronic Edition (ACM DL) BibTeX
- Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr:
Instruction encoding synthesis for architecture exploration using hierarchical processor models.
262-267
Electronic Edition (ACM DL) BibTeX
Nano technology:
design implications and CAD challenges
Mixed signals on mixed-signal:
the right next technology
Simulation coverage and generation for verification
Tool support for architectural decisions in embedded systems
New topics in logic synthesis
Coping with variability:
the end of deterministic design
Fast,
cheap and under control:
the next implementation fabric
Testbench,
verification and debugging:
practical considerations
- Serdar Tasiran, Yuan Yu, Brannon Batson:
Using a formal specification and a model checker to monitor and direct simulation.
356-361
Electronic Edition (ACM DL) BibTeX
- Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai:
Advanced techniques for RTL debugging.
362-367
Electronic Edition (ACM DL) BibTeX
- Edmund M. Clarke, Daniel Kroening, Karen Yorav:
Behavioral consistency of C and verilog programs using bounded model checking.
368-371
Electronic Edition (ACM DL) BibTeX
- Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker:
Re-use-centric architecture for a fully accelerated testbench environment.
372-375
Electronic Edition (ACM DL) BibTeX
Delay and noise modeling in the nanometer regime
Modeling issues in the design of embedded systems
How application/technology evolutions will shape classical EDA?
SAT and BDD algorithms for verification tools
- Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Bryant:
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions.
425-430
Electronic Edition (ACM DL) BibTeX
- Amit Goel, Gagan Hasteer, Randal E. Bryant:
Symbolic representation with ordered function templates.
431-435
Electronic Edition (ACM DL) BibTeX
- Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna:
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
436-441
Electronic Edition (ACM DL) BibTeX
- Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain:
Solving the latch mapping problem in an industrial setting.
442-447
Electronic Edition (ACM DL) BibTeX
Elements of functional and performance analysis
Nonlinear model order reduction
Novel techniques in high-level synthesis
Mixed-signal design and simulation
- Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown:
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference.
520-525
Electronic Edition (ACM DL) BibTeX
- Charlotte Y. Lau, Michael H. Perrott:
Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm.
526-531
Electronic Edition (ACM DL) BibTeX
- Payam Heydari:
Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators.
532-537
Electronic Edition (ACM DL) BibTeX
- Vinita Vasudevan, M. Ramakrishna:
Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique.
538-541
Electronic Edition (ACM DL) BibTeX
- Alicia Manthe, Zhao Li, C.-J. Richard Shi:
Symbolic analysis of analog circuits with hard nonlinearity.
542-545
Electronic Edition (ACM DL) BibTeX
Nanometer design:
place your bets
Novel self-test methods
- Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey:
A scalable software-based self-test methodology for programmable processors.
548-553
Electronic Edition (ACM DL) BibTeX
- Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
A scan BIST generation method using a markov source and partial bit-fixing.
554-559
Electronic Edition (ACM DL) BibTeX
- Ahmad A. Al-Yamani, Edward J. McCluskey:
Seed encoding with LFSRs and cellular automata.
560-565
Electronic Edition (ACM DL) BibTeX
- Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin:
Efficient compression and application of deterministic patterns in a logic BIST architecture.
566-569
Electronic Edition (ACM DL) BibTeX
- Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
Ultimate low cost analog BIST.
570-573
Electronic Edition (ACM DL) BibTeX
Technology mapping,
buffering,
and bus design
Compilation techniques for reconfigurable devices
Architectural power estimation and optimization
- Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii:
Clock-tree power optimization based on RTL clock-gating.
622-627
Electronic Edition (ACM DL) BibTeX
- Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Low-power design methodology for an on-chip bus with adaptive bandwidth capability.
628-633
Electronic Edition (ACM DL) BibTeX
- Tali Moreshet, R. Iris Bahar:
Power-aware issue queue design for speculative instructions.
634-637
Electronic Edition (ACM DL) BibTeX
- Reinaldo A. Bergamaschi, Yunjian Jiang:
State-based power analysis for systems-on-chip.
638-641
Electronic Edition (ACM DL) BibTeX
- Carl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar:
Libraries: lifejacket or straitjacket.
642-643
Electronic Edition (ACM DL) BibTeX
Libraries:
Lifejacket or straitjacket
Techniques for reconfigurable logic applications
Test and diagnosis for complex designs
Highlights of ISSCC:
high-speed heterogeneous design techniques
- Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong:
Design of a 10GHz clock distribution network using coupled standing-wave oscillators.
682-687
Electronic Edition (ACM DL) BibTeX
- John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas:
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL.
688-690
Electronic Edition (ACM DL) BibTeX
- Michele Borgatti, L. Cali, Guido De Sandre, B. Forét, D. Iezzi, Francesco Lertora, G. Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi:
A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory.
691-695
Electronic Edition (ACM DL) BibTeX
Highlights of ISSCC and the design of state-of-the-art microprocessors
- Yiu-Hing Chan, Prabhakar Kudva, Lisa B. Lacey, Gregory A. Northrop, Thomas E. Rosser:
Physical synthesis methodology for high performance microprocessors.
696-701
Electronic Edition (ACM DL) BibTeX
- Hisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama:
A 1.3GHz fifth generation SPARC64 microprocessor.
702-705
Electronic Edition (ACM DL) BibTeX
- Jason Stinson, Stefan Rusu:
A 1.5GHz third generation itanium® 2 processor.
706-709
Electronic Edition (ACM DL) BibTeX
Formal verification - prove it or pitch it
High frequency interconnect modeling
- Zhenhai Zhu, Ben Song, Jacob White:
Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-D geometries.
712-717
Electronic Edition (ACM DL) BibTeX
- Hao Yu, Lei He:
Vector potential equivalent circuit based on PEEC inversion.
718-723
Electronic Edition (ACM DL) BibTeX
- David Goren, Michael Zelikson, Rachel Gordin, Israel A. Wagner, Anastasia Barger, Alon Amir, Betty Livshitz, Anatoly Sherman, Youri Tretiakov, Robert A. Groves, J. Park, Donald L. Jordan, Sue E. Strang, Raminderpal Singh, Carl E. Dickey, David L. Harame:
On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices.
724-727
Electronic Edition (ACM DL) BibTeX
- Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy:
An adaptive window-based susceptance extraction and its efficient implementation.
728-731
Electronic Edition (ACM DL) BibTeX
Novel approaches in test coast reduction
Retargetable tools for embedded software
ASIC design in nanometer era - dead or alive?
- David E. Lackey, Paul S. Zuchowski, Jürgen Koehl:
Designing mega-ASICs in nanogate technologies.
770-775
Electronic Edition (ACM DL) BibTeX
- Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind:
Architecting ASIC libraries and flows in nanometer era.
776-781
Electronic Edition (ACM DL) BibTeX
- Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, V. Rovner, K. Y. Tong:
Exploring regular fabrics to optimize the performance-cost trade-off.
782-787
Electronic Edition (ACM DL) BibTeX
- Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni:
Pushing ASIC performance in a power envelope.
788-793
Electronic Edition (ACM DL) BibTeX
Floorplanning and placement
- Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu:
An algebraic multigrid solver for analytical placement with layout based clustering.
794-799
Electronic Edition (ACM DL) BibTeX
- Bo Hu, Malgorzata Marek-Sadowska:
Wire length prediction based clustering and its application in placement.
800-805
Electronic Edition (ACM DL) BibTeX
- Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
806-811
Electronic Edition (ACM DL) BibTeX
- Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang:
Multilevel floorplanning/placement for large-scale modules using B*-trees.
812-817
Electronic Edition (ACM DL) BibTeX
Advances in SAT
Novel design methodologies and signal integrity
- Gilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Satish Iyengar, Alain Pirson:
Design of a 17-million gate network processor using a design factory.
844-849
Electronic Edition (ACM DL) BibTeX
- Kaijian Shi, Graig Godwin:
Hybrid hierarchical timing closure methodology for a high performance and low power DSP.
850-855
Electronic Edition (ACM DL) BibTeX
- Imad A. Ferzli, Farid N. Najm:
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations.
856-859
Electronic Edition (ACM DL) BibTeX
- Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Temporofunctional crosstalk noise analysis.
860-863
Electronic Edition (ACM DL) BibTeX
- Ken Tseng, Vinod Kariat:
Static noise analysis with noise windows.
864-868
Electronic Edition (ACM DL) BibTeX
Memory optimization for embedded systems
Design automation for quantum circuits
Energy-aware system design
Budgeting,
simulation and statistical timing
Interconnect noise avoidance methodologies & slew rate prediction
Analog design space exploration
Copyright © Sat May 16 23:04:38 2009
by Michael Ley (ley@uni-trier.de)
