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40. DAC 2003: Anaheim, CA, USA

Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003. ACM 2003, ISBN 1-58113-688-9 BibTeX
  title     = {Proceedings of the 40th Design Automation Conference, DAC 2003,
               Anaheim, CA, USA, June 2-6, 2003},
  booktitle = {DAC},
  publisher = {ACM},
  year      = {2003},
  isbn      = {1-58113-688-9},
  bibsource = {DBLP, http://dblp.uni-trier.de}

Real challenges and solutions for validating system-on-chip

Reshaping EDA for power

Design for manufacturability and global routing

Design analysis techniques

Embedded hardware design case studies

Emerging design and tool challenges in RF and wireless applications

COT-customer owned trouble

Low-power embedded system design

Cyclic and non-cyclic combinational circuit synthesis

Managing leakage power

Emerging markets: design goes global

Model order reduction

Issues in partitioning & design space epolartion for codesign

Nano technology: design implications and CAD challenges

Mixed signals on mixed-signal: the right next technology

Simulation coverage and generation for verification

Tool support for architectural decisions in embedded systems

New topics in logic synthesis

Coping with variability: the end of deterministic design

Fast, cheap and under control: the next implementation fabric

Testbench, verification and debugging: practical considerations

Delay and noise modeling in the nanometer regime

Modeling issues in the design of embedded systems

How application/technology evolutions will shape classical EDA?

SAT and BDD algorithms for verification tools

Elements of functional and performance analysis

Nonlinear model order reduction

Novel techniques in high-level synthesis

Mixed-signal design and simulation

Nanometer design: place your bets

Novel self-test methods

Technology mapping, buffering, and bus design

Compilation techniques for reconfigurable devices

Architectural power estimation and optimization

Libraries: Lifejacket or straitjacket

Techniques for reconfigurable logic applications

Test and diagnosis for complex designs

Highlights of ISSCC: high-speed heterogeneous design techniques

Highlights of ISSCC and the design of state-of-the-art microprocessors

Formal verification - prove it or pitch it

High frequency interconnect modeling

Novel approaches in test coast reduction

Retargetable tools for embedded software

ASIC design in nanometer era - dead or alive?

Floorplanning and placement

Advances in SAT

Novel design methodologies and signal integrity

Memory optimization for embedded systems

Design automation for quantum circuits

Energy-aware system design

Budgeting, simulation and statistical timing

Interconnect noise avoidance methodologies & slew rate prediction

Analog design space exploration

Copyright © Sat May 16 23:04:38 2009 by Michael Ley (ley@uni-trier.de)