| 2005 |
|---|
| 8 | EE | Hyeong-Ju Kang,
In-Cheol Park:
SAT-based unbounded symbolic model checking.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 129-140 (2005) |
| 2003 |
|---|
| 7 | EE | Hyeong-Ju Kang,
In-Cheol Park:
SAT-based unbounded symbolic model checking.
DAC 2003: 840-843 |
| 6 | EE | Sung-Won Lee,
Hyeong-Ju Kang,
In-Cheol Park:
A 24-bit floating-point audio DSP controller supporting fast exponentiation.
ISCAS (2) 2003: 748-751 |
| 5 | EE | Hyeong-Ju Kang,
In-Cheol Park:
Pairing and ordering to reduce hardware complexity in cascade form filter design.
ISCAS (4) 2003: 265-268 |
| 2002 |
|---|
| 4 | EE | In-Cheol Park,
Hyeong-Ju Kang:
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1525-1529 (2002) |
| 2001 |
|---|
| 3 | EE | In-Cheol Park,
Hyeong-Ju Kang:
Digital Filter Synthesis Based on Minimal Signed Digit Representation.
DAC 2001: 468-473 |
| 2 | EE | Hyeong-Ju Kang,
In-Cheol Park:
Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders.
ISCAS (2) 2001: 693-696 |
| 2000 |
|---|
| 1 | | Hyeong-Ju Kang,
Hansoo Kim,
In-Cheol Park:
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders.
ICCAD 2000: 51-54 |
