2008 | ||
---|---|---|
53 | EE | Carl Christian Rolf, Krzysztof Kuchcinski: Load-balancing methods for parallel and distributed constraint solving. CLUSTER 2008: 304-309 |
52 | EE | Christophe Wolinski, Krzysztof Kuchcinski: Automatic Selection of Application-Specific Reconfigurable Processor Extensions. DATE 2008: 1214-1219 |
51 | EE | Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM 2008: 306-309 |
50 | EE | Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL 2008: 391-396 |
49 | EE | Carl Christian Rolf, Krzysztof Kuchcinski: State-copying and Recomputation in Parallel Constraint Programming with Global Constraints. PDP 2008: 311-317 |
2007 | ||
48 | EE | Christophe Wolinski, Krzysztof Kuchcinski: Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints. ASAP 2007: 328-333 |
47 | EE | Ana Fuentes Martinez, Krzysztof Kuchcinski: Graph Matching Constraints for Synthesis with Complex Components. DSD 2007: 288-295 |
46 | Christophe Wolinski, Krzysztof Kuchcinski: Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware. ERSA 2007: 175-181 | |
45 | EE | Mats Petter Pettersson, Krzysztof Kuchcinski: A New Necessary Condition for Shortest Path Routing. NET-COOP 2007: 195-204 |
44 | EE | Mats Petter Pettersson, Radoslaw Szymanek, Krzysztof Kuchcinski: A CP-LP approach to network management in OSPF routing. SAC 2007: 311-315 |
2006 | ||
43 | EE | Ali R. Iranpour, Krzysztof Kuchcinski: Performance Improvement for H.264 Video Encoding using ILP Embedded Processor. DSD 2006: 515-521 |
42 | EE | Ali R. Iranpour, Krzysztof Kuchcinski: Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors. SAMOS 2006: 309-320 |
2005 | ||
41 | EE | Per Andersson, Krzysztof Kuchcinski: Java to Hardware Compilation for non Data Flow Applications. DSD 2005: 330-337 |
40 | EE | Christophe Wolinski, Krzysztof Kuchcinski: A Constraints Programming Approach for Fabric Cell Synthesis. DSD 2005: 356-363 |
39 | EE | Henrik Svensson, Viktor Öwall, Krzysztof Kuchcinski: Implementation aspects of a novel speech packet loss concealment method. ISCAS (3) 2005: 2867-2870 |
38 | EE | Flavius Gruian, Per Andersson, Krzysztof Kuchcinski, Martin Schoeberl: Automatic generation of application-specific systems based on a micro-programmed Java core. SAC 2005: 879-884 |
2004 | ||
37 | EE | Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuchcinski: Time-Energy Design Space Exploration for Multi-Layer Memory Architectures. DATE 2004: 318-323 |
36 | EE | Ali R. Iranpour, Krzysztof Kuchcinski: Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4. DSD 2004: 262-269 |
35 | EE | Christophe Wolinski, Krzysztof Kuchcinski, Maya Gokhale: A Constraints Programming Approach to Communication Scheduling on SoPC Architectures. DSD 2004: 308-315 |
34 | Per Andersson, Krzysztof Kuchcinski: Distinguished Paper: Automatic Local Memory Architecture Generation for Data Reuse in Custom Data Paths. ERSA 2004: 137-144 | |
33 | Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuchcinski: Data assignment and access scheduling exploration for multi-layer memory architectures. ESTImedia 2004: 61-66 | |
32 | EE | Christophe Wolinski, Krzysztof Kuchcinski, Maya Gokhale: A constraints programming approach to communication scheduling on SoPC architectures. FPGA 2004: 252 |
2003 | ||
31 | EE | Radoslaw Szymanek, Krzysztof Kuchcinski: Partial task assignment of task graphs under heterogeneous resource constraints. DAC 2003: 244-249 |
30 | EE | Flavius Gruian, Krzysztof Kuchcinski: Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time. ISLPED 2003: 465-468 |
29 | EE | Krzysztof Kuchcinski: Constraints-driven scheduling and resource assignment. ACM Trans. Design Autom. Electr. Syst. 8(3): 355-383 (2003) |
28 | EE | Krzysztof Kuchcinski, Christophe Wolinski: Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming. Journal of Systems Architecture 49(12-15): 489-503 (2003) |
2002 | ||
27 | EE | Per Andersson, Krzysztof Kuchcinski, Klas Nordberg, Patrick Doherty: Integrating a Computational Model and a Run Time System for Image Processing on a UAV. DSD 2002: 102-109 |
2001 | ||
26 | EE | Flavius Gruian, Krzysztof Kuchcinski: LEneS: task scheduling for low-energy systems using variable supply voltage processors. ASP-DAC 2001: 449-455 |
25 | EE | Radoslaw Szymanek, Krzysztof Kuchcinski: A constructive algorithm for memory-aware task assignment and scheduling. CODES 2001: 147-152 |
24 | EE | Krzysztof Kuchcinski, Christophe Wolinski: Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming. DSD 2001: 220-227 |
2000 | ||
23 | Patrik Dohrty, Gösta H. Granlund, Krzysztof Kuchcinski, Erik Sandewall, Klas Nordberg, Erik Skarman, Johan Wiklund: The WITAS Unmanned Aerial Vehicle Project. ECAI 2000: 747-755 | |
22 | EE | Per Andersson, Krzysztof Kuchcinski: Performance Oriented Partitioning for Time-Multiplexed FPGA's. EUROMICRO 2000: 1060-1066 |
21 | EE | Radoslaw Szymanek, Krzysztof Kuchcinski: Task Assignment and Scheduling under Memory Constraints. EUROMICRO 2000: 1084-1090 |
1999 | ||
20 | EE | Krzysztof Kuchcinski: Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain Constraints. DATE 1999: 772-773 |
19 | EE | Krzysztof Kuchcinski: Synthesis of Distributed Embedded Systems. EUROMICRO 1999: 1022-1028 |
18 | EE | Radoslaw Szymanek, Krzysztof Kuchcinski: Design Space Exploration in System Level Synthesis under Memory Constraints. EUROMICRO 1999: 1029- |
17 | EE | Flavius Gruian, Krzysztof Kuchcinski: Low-Energy Directed Architecture Selection and Task Scheduling for System-Level Design. EUROMICRO 1999: 1296-1302 |
1998 | ||
16 | EE | Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop: Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. DATE 1998: 132- |
15 | EE | Krzysztof Kuchcinski: An Approach to High-Level Synthesis Using Constraint Logic Programming. EUROMICRO 1998: 10074-10082 |
14 | EE | Flavius Gruian, Krzysztof Kuchcinski: Operation Binding and Scheduling for Low Power Using Constraint Logic Programming. EUROMICRO 1998: 10083-10090 |
13 | EE | Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop: Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems. EUROMICRO 1998: 10168- |
1997 | ||
12 | EE | Xinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo Peng: A controller testability analysis and enhancement technique. ED&TC 1997: 153-157 |
11 | EE | Krzysztof Kuchcinski: Embedded System Synthesis by Timing Constraints Solving. ISSS 1997: 50-57 |
1996 | ||
10 | EE | Peter Grün, Petru Eles, Krzysztof Kuchcinski, Zebo Peng: Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis. EUROMICRO 1996: 185-192 |
9 | EE | Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli: Hardware/Software Partitioning with Iterative Improvement Heuristics. ISSS 1996: 71-76 |
8 | EE | Petru Eles, Krzysztof Kuchcinski, Zebo Peng: Synthesis of systems specified as interacting VHDL processes. Integration 21(1-2): 113-138 (1996) |
1995 | ||
7 | EE | Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli: Timing constraint specification and synthesis in behavioral VHDL. EURO-DAC 1995: 452-457 |
6 | Xinli Gu, Krzysztof Kuchcinski, Zebo Peng: An Efficient and Economic Partitioning Approach for Testability. ITC 1995: 403-412 | |
1994 | ||
5 | EE | Petru Eles, Marius Minea, Krzysztof Kuchcinski, Zebo Peng: Synthesis of VHDL concurrent processes. EURO-DAC 1994: 540-545 |
4 | EE | Xinli Gu, Krzysztof Kuchcinski, Zebo Peng: Testability analysis and improvement from VHDL behavioral specifications. EURO-DAC 1994: 644-649 |
3 | EE | Zebo Peng, Krzysztof Kuchcinski: Automated transformation of algorithms into register-transfer level implementations. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 150-166 (1994) |
1993 | ||
2 | Krzysztof Kuchcinski, Wlodzimierz Drabent, Jan Maluszynski: Automatic Diagnosis of VLSI Digital Circuits Using Algorithmic Debugging. AADEBUG 1993: 350-367 | |
1988 | ||
1 | EE | Krzysztof Kuchcinski, Bogdan Wiszniewski: Path analysis of distributed programs. ACM Conference on Computer Science 1988: 320-328 |