Tsutomu Sasao

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106EEHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura: A Parallel Branching Program Machine for Emulation of Sequential Circuits. ARC 2009: 261-267
105EEShinobu Nagayama, Tsutomu Sasao: Complexities of Graph-Based Representations for Elementary Functions. IEEE Trans. Computers 58(1): 106-119 (2009)
104EEShinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Numerical function generators using bilinear interpolation. FPL 2008: 463-466
103EETsutomu Sasao: On the numbers of variables to represent sparse logic functions. ICCAD 2008: 45-51
102EEShinobu Nagayama, Tsutomu Sasao: Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators. ISMVL 2008: 50-56
101EETsutomu Sasao: On the Complexity of Classification Functions. ISMVL 2008: 57-63
100EEShinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. ASP-DAC 2007: 535-540
99EEShinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. DSD 2007: 280-287
98EETsutomu Sasao, Munehiro Matsuura: An Implementation of an Address Generator Using Hash Memories. DSD 2007: 69-76
97EEHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A CAM Emulator Using Look-Up Table Cascades. IPDPS 2007: 1-8
96EEYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. ISMVL 2007: 32
95EETsutomu Sasao: An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays. ISMVL 2007: 40
94EEShinobu Nagayama, Tsutomu Sasao: Representations of Elementary Functions Using Edge-Valued MDDs. ISMVL 2007: 5
93EETsutomu Sasao, Shinobu Nagayama, Jon T. Butler: Numerical Function Generators Using LUT Cascades. IEEE Trans. Computers 56(6): 826-838 (2007)
92EEShinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs. IEICE Transactions 90-A(12): 2752-2761 (2007)
91EEMunehiro Matsuura, Tsutomu Sasao: BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades. IEICE Transactions 90-A(12): 2762-2769 (2007)
90EEDebatosh Debnath, Tsutomu Sasao: A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks. IEICE Transactions 90-A(5): 932-940 (2007)
89EEYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Design Methods of Radix Converters Using Arithmetic Decompositions. IEICE Transactions 90-D(6): 905-914 (2007)
88EEHui Qin, Tsutomu Sasao, Jon T. Butler: Implementation of LPM Address Generators on FPGAs. ARC 2006: 170-181
87EEShinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. ASP-DAC 2006: 378-383
86EEHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A fast logic simulator using a look up table cascade emulator. ASP-DAC 2006: 466-472
85EETsutomu Sasao: Design Methods for Multiple-Valued Input Address Generators. ISMVL 2006: 1
84EETsutomu Sasao, Jon T. Butler: Implementation of Multiple-Valued CAM Functions by LUT Cascades. ISMVL 2006: 11
83EETsutomu Sasao, Shinobu Nagayama: Representations of Elementary Functions Using Binary Moment Diagrams. ISMVL 2006: 28
82EEYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On Designs of Radix Converters Using Arithmetic Decompositions. ISMVL 2006: 3
81EEDebatosh Debnath, Tsutomu Sasao: Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries. IEICE Transactions 89-A(12): 3443-3450 (2006)
80EEHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. IEICE Transactions 89-A(12): 3471-3481 (2006)
79EEShinobu Nagayama, Tsutomu Sasao, Jon T. Butler: Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method. IEICE Transactions 89-A(12): 3510-3518 (2006)
78EEHui Qin, Tsutomu Sasao, Yukihiro Iguchi: A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA. IEICE Transactions 89-D(3): 1139-1147 (2006)
77EEHui Qin, Tsutomu Sasao, Yukihiro Iguchi: An FPGA design of AES encryption circuit with 128-bit keys. ACM Great Lakes Symposium on VLSI 2005: 147-151
76EETsutomu Sasao, Munehiro Matsuura: BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. DAC 2005: 373-378
75EETsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki: On LUT Cascade Realizations of FIR Filters. DSD 2005: 467-475
74 Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler: Programmable Numerical Function Generators: Architectures and Synthesis Method. FPL 2005: 118-123
73EEMarek A. Perkowski, Tsutomu Sasao, Jong-Hwan Kim, Martin Lukac, Jeff Allen, Stefan Gebauer: Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem. ISMVL 2005: 236-248
72EETsutomu Sasao: Radix Converters: Complexity and Implementation by LUT Cascades. ISMVL 2005: 256-263
71EEYukihiro Iguchi, Tsutomu Sasao: Hardware to Compute Walsh Coefficients. ISMVL 2005: 75-81
70EEJon T. Butler, Tsutomu Sasao, Munehiro Matsuura: Average Path Length of Binary Decision Diagrams. IEEE Trans. Computers 54(9): 1041-1053 (2005)
69EEShinobu Nagayama, Tsutomu Sasao: On the optimization of heterogeneous MDDs. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1645-1659 (2005)
68EEDebatosh Debnath, Tsutomu Sasao: Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs. IEICE Transactions 88-A(12): 3332-3341 (2005)
67EEHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Design Algorithm for Sequential Circuits Using LUT Rings. IEICE Transactions 88-A(12): 3342-3350 (2005)
66EEDebatosh Debnath, Tsutomu Sasao: Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders. IEICE Transactions 88-D(7): 1492-1500 (2005)
65EETsutomu Sasao, Jon T. Butler: A fast method to derive minimum SOPs for decomposable functions. ASP-DAC 2004: 585-590
64EEDebatosh Debnath, Tsutomu Sasao: Efficient computation of canonical form for Boolean matching in large libraries. ASP-DAC 2004: 591-596
63EEShinobu Nagayama, Tsutomu Sasao: Minimization of memory size for heterogeneous MDDs. ASP-DAC 2004: 871-874
62EETsutomu Sasao, Munehiro Matsuura: A method to decompose multiple-output logic functions. DAC 2004: 428-433
61EEShinobu Nagayama, Tsutomu Sasao: On the Minimization of Average Path Lengths for Heterogeneous MDDs. ISMVL 2004: 216-222
60EEYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. ISMVL 2004: 302-308
59EEAlan Mishchenko, Tsutomu Sasao: Large-scale SOP minimization using decomposition and functional properties. DAC 2003: 149-154
58EETsutomu Sasao: Cascade Realizations of Two-valued Input Multiple-Valued Output Functions using Decomposition of Group Functions. ISMVL 2003: 125-132
57EEShinobu Nagayama, Tsutomu Sasao: Compact Representations of Logic Functions using Heterogeneous MDDs. ISMVL 2003: 247-252
56EEJon T. Butler, Tsutomu Sasao: On the Average Path Length in Decision Diagrams of Multiple-Valued Functions. ISMVL 2003: 383-390
55EEShinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura: Representations of Logic Functions Using QRMDDs. ISMVL 2002: 261-
54 Alan Mishchenko, Tsutomu Sasao: Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. IWLS 2002: 115-120
53 Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura: Comparison of Decision Diagrams for Multiple-Output Logic Functions. IWLS 2002: 379-384
52EETsutomu Sasao, Jon T. Butler: On the minimization of SOPs for bi-decomposition functions. ASP-DAC 2001: 219-224
51 Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Realization of Multiple-Output Functions by Reconfigurable Cascades. ICCD 2001: 388-393
50 Tsutomu Sasao: Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic. ISMVL 2001: 207-212
49EETsutomu Sasao, Jon T. Butler: Worst and Best Irredundant Sum-of-Products Expressions. IEEE Trans. Computers 50(9): 935-948 (2001)
48EERadomir S. Stankovic, Tsutomu Sasao: A discussion on the history of research in arithmetic andReed-Muller expressions. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1177-1179 (2001)
47EEDebatosh Debnath, Tsutomu Sasao: Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions. ASP-DAC 2000: 247-252
46EETsutomu Sasao, Ken-ichi Kurimoto: Three parameters to find functional decompositions. ASP-DAC 2000: 259-264
45EEYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno: A hardware simulation engine based on decision diagrams (short paper). ASP-DAC 2000: 73-76
44EEHafiz Md. Hasan Babu, Tsutomu Sasao: Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. ISMVL 2000: 147-152
43EEYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Implementation of Multiple-Output Functions Using PQMDDs. ISMVL 2000: 199-205
42EETsutomu Sasao: On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions. ISMVL 2000: 91-
41 Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy: Selection of potentially testable path delay faults for test generation. ITC 2000: 376-384
40EEYukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno: Realization of Regular Ternary Logic Functions. ASP-DAC 1999: 331-
39EEDebatosh Debnath, Tsutomu Sasao: Fast Boolean Matching Under Permutation Using Representative. ASP-DAC 1999: 359-362
38EEHafiz Md. Hasan Babu, Tsutomu Sasao: Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions. ISMVL 1999: 166-172
37EETsutomu Sasao: Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions. ISMVL 1999: 59-65
36EEDebatosh Debnath, Tsutomu Sasao: Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates. ISMVL 1999: 99-104
35 Radomir S. Stankovic, Tsutomu Sasao: Decision Diagrams for Discrete Functions: Classification and Unified Interpretation. ASP-DAC 1998: 439-446
34 Debatosh Debnath, Tsutomu Sasao: A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks. ASP-DAC 1998: 69-74
33EEHafiz Md. Hasan Babu, Tsutomu Sasao: Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. ISMVL 1998: 45-51
32EEJon T. Butler, Tsutomu Sasao: On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. ISMVL 1998: 83-88
31EESeiji Kajihara, Tsutomu Sasao: On the Adders with Minimum Tests. Asian Test Symposium 1997: 10-15
30EEYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On Decomposition of Kleene TDDs. Asian Test Symposium 1997: 234-
29EETsutomu Sasao: Ternary Decision Diagrams: Survey. ISMVL 1997: 241-
28EETsutomu Sasao, Jon T. Butler: Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. ISMVL 1997: 55-60
27 Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III: Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. IEEE Trans. Computers 46(4): 491-494 (1997)
26 Tsutomu Sasao: Easily Testable Realizations for Generalized Reed-Muller Expressions. IEEE Trans. Computers 46(6): 709-716 (1997)
25EEJon T. Butler, J. L. Nowlin, Tsutomu Sasao: Planarity in ROMDD's of Multiple-Valued Symmetric Functions. ISMVL 1996: 236-241
24EETsutomu Sasao, Jon T. Butler: A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. ISMVL 1996: 248-254
23EEDebatosh Debnath, Tsutomu Sasao: GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions. ASP-DAC 1995
22EETsutomu Sasao, Jon T. Butler: Planar Multiple-Valued Decision Diagrams. ISMVL 1995: 28-35
21 Jon T. Butler, Tsutomu Sasao: Multiple-Valued Combinational Circuits with Feedback. ISMVL 1994: 342-347
20 Radomir S. Stankovic, Milena Stankovic, Claudio Moraga, Tsutomu Sasao: Calculation of Reed-Muller-Fourier Coefficients of Multiple-Valued Functions through Multiple-Place Decision Diagrams. ISMVL 1994: 82-88
19 Tsutomu Sasao, Jon T. Butler: A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. ISMVL 1994: 97-106
18 Daniel Brand, Tsutomu Sasao: Minimization of AND-EXOR Expressions Using Rewrite Rules. IEEE Trans. Computers 42(5): 568-576 (1993)
17EETsutomu Sasao: EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 621-632 (1993)
16 Tsutomu Sasao: Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams. ISMVL 1992: 451-458
15 Tsutomu Sasao: A Transformation of Multiple-Valued Input Two-Valued Output Functions and its Application to Simplification of Exclusive-or Sum-of-Products Expressions. ISMVL 1991: 270-279
14 Tsutomu Sasao: Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions. IEEE Trans. Computers 40(5): 645-651 (1991)
13 Tsutomu Sasao: EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions. ISMVL 1990: 128-135
12 Tsutomu Sasao: On the Optimal Design of Multiple-Valued PLA's. IEEE Trans. Computers 38(4): 582-592 (1989)
11 Tsutomu Sasao: Multiple-Valued Logic and Optimization of Programmable Logic Arrays. IEEE Computer 21(4): 71-80 (1988)
10EETsutomu Sasao: MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators. DAC 1986: 86-93
9 Tsutomu Sasao: An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs. IEEE Trans. Computers 34(2): 131-140 (1985)
8 Tsutomu Sasao: Input Variable Assignment and Output Phase Optimization of PLA's. IEEE Trans. Computers 33(10): 879-894 (1984)
7 Tsutomu Sasao: Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays. IEEE Trans. Computers 30(9): 635-643 (1981)
6 Tsutomu Sasao, Kozo Kinoshita: On the Number of Fanout-Free Functions and Unate Cascade Functions. IEEE Trans. Computers 28(1): 66-72 (1979)
5 Tsutomu Sasao, Kozo Kinoshita: Conservative Logic Elements and Their Universality. IEEE Trans. Computers 28(9): 682-685 (1979)
4 Tsutomu Sasao, Kozo Kinoshita: Cascade Realization of 3-Input 3-Output Conservative Logic Circuits. IEEE Trans. Computers 27(3): 214-221 (1978)
3 Tsutomu Sasao, Kozo Kinoshita: Realization of Minimum Circuits with Two-Input Conservative Logic Elements. IEEE Trans. Computers 27(8): 749-752 (1978)
2 Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda: On Magnetic Bubble Logic Circuits. IEEE Trans. Computers 25(3): 247-253 (1976)
1 Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita: Easily Testable Sequential Machines with Extra Inputs. IEEE Trans. Computers 24(8): 821-826 (1975)

Coauthor Index

1Jeff Allen [73]
2Hafiz Md. Hasan Babu [33] [38] [44]
3Robert J. Barton III [27]
4Daniel Brand [18]
5Jon T. Butler [19] [21] [22] [24] [25] [27] [28] [32] [49] [52] [56] [65] [70] [74] [79] [84] [87] [88] [92] [93] [99] [100] [104]
6Debatosh Debnath [23] [34] [36] [39] [47] [64] [66] [68] [81] [90]
7Hideo Fujiwara [1]
8Stefan Gebauer [73]
9David S. Herscovici [27]
10Yukihiro Iguchi [30] [40] [43] [45] [51] [53] [55] [60] [71] [75] [77] [78] [82] [89] [96]
11Atsumu Iseno [40] [45]
12Seiji Kajihara [31] [41]
13Yoshifumi Kawamura [106]
14Jong-Hwan Kim [73]
15Kozo Kinoshita [1] [2] [3] [4] [5] [6]
16Ken-ichi Kurimoto [46]
17Martin Lukac [73]
18Jun Matsuda [2]
19Munehiro Matsuura [30] [40] [43] [45] [51] [53] [55] [60] [62] [67] [70] [76] [80] [82] [86] [89] [91] [96] [97] [98] [106]
20Alan Mishchenko [54] [59]
21Claudio Moraga [20]
22Atsushi Murakami [41]
23Yoich Nagao [1]
24Shinobu Nagayama [55] [57] [61] [63] [69] [74] [79] [83] [87] [92] [93] [94] [99] [100] [102] [104] [105]
25Hiroki Nakahara [67] [80] [86] [97] [106]
26J. L. Nowlin [25]
27Marek A. Perkowski [73]
28Irith Pomeranz [41]
29Hui Qin [77] [78] [88]
30Sudhakar M. Reddy [41]
31Milena Stankovic [20]
32Radomir S. Stankovic [20] [35] [48]
33Takahiro Suzuki [75]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)