| 2006 |
|---|
| 11 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
Designing via-configurable logic blocks for regular fabric.
IEEE Trans. VLSI Syst. 14(1): 1-14 (2006) |
| 10 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics.
IEEE Trans. VLSI Syst. 14(9): 998-1009 (2006) |
| 2005 |
|---|
| 9 | | Yajun Ran,
Malgorzata Marek-Sadowska:
Via-configurable routing architectures and fast design mappability estimation for regular fabrics.
ICCAD 2005: 25-32 |
| 8 | EE | Kai Wang,
Yajun Ran,
Hailin Jiang,
Malgorzata Marek-Sadowska:
General skew constrained clock network sizing based on sequential linear programming.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 773-782 (2005) |
| 7 | EE | Yajun Ran,
Alex Kondratyev,
Kenneth H. Tseng,
Yosinori Watanabe,
Malgorzata Marek-Sadowska:
Eliminating false positives in crosstalk noise analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1406-1419 (2005) |
| 2004 |
|---|
| 6 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
On designing via-configurable cell blocks for regular fabrics.
DAC 2004: 198-203 |
| 5 | EE | Yajun Ran,
Alex Kondratyev,
Yosinori Watanabe,
Malgorzata Marek-Sadowska:
Eliminating False Positives in Crosstalk Noise Analysis.
DATE 2004: 1192-1197 |
| 4 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
An integrated design flow for a via-configurable gate array.
ICCAD 2004: 582-589 |
| 3 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
The Magic of a Via-Configurable Regular Fabric.
ICCD 2004: 338-343 |
| 2003 |
|---|
| 2 | EE | Donald Chai,
Alex Kondratyev,
Yajun Ran,
Kenneth H. Tseng,
Yosinori Watanabe,
Malgorzata Marek-Sadowska:
Temporofunctional crosstalk noise analysis.
DAC 2003: 860-863 |
| 1 | EE | Yajun Ran,
Malgorzata Marek-Sadowska:
Crosstalk noise in FPGAs.
DAC 2003: 944-949 |
