2006 |
17 | EE | Jianjiang Ceng,
Weihua Sheng,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
VLSI Signal Processing 43(2-3): 235-246 (2006) |
2005 |
16 | EE | Jianjiang Ceng,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun:
C Compiler Retargeting Based on Instruction Semantics Models.
DATE 2005: 1150-1155 |
2004 |
15 | EE | Gunnar Braun,
Achim Nohl,
Weihua Sheng,
Jianjiang Ceng,
Manuel Hohenauer,
Hanno Scharwächter,
Rainer Leupers,
Heinrich Meyr:
A novel approach for flexible and consistent ADL-driven ASIP design.
DAC 2004: 717-722 |
14 | EE | Andreas Wieferink,
Tim Kogel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun,
Achim Nohl:
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.
DATE 2004: 1256-1263 |
13 | EE | Manuel Hohenauer,
Hanno Scharwächter,
Kingshuk Karuri,
Oliver Wahlen,
Tim Kogel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun,
Hans van Someren:
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.
DATE 2004: 1276-1283 |
12 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Mario Steinert,
Gunnar Braun,
Achim Nohl:
RTL Processor Synthesis for Architecture Exploration and Implementation.
DATE 2004: 156-160 |
11 | EE | Jianjiang Ceng,
Weihua Sheng,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
SAMOS 2004: 463-473 |
10 | EE | Gunnar Braun,
Achim Nohl,
Andreas Hoffmann,
Oliver Schliebusch,
Rainer Leupers,
Heinrich Meyr:
A universal technique for fast and flexible instruction-set architecture simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1625-1639 (2004) |
2003 |
9 | EE | Achim Nohl,
Volker Greive,
Gunnar Braun,
Andreas Hoffmann,
Rainer Leupers,
Oliver Schliebusch,
Heinrich Meyr:
Instruction encoding synthesis for architecture exploration using hierarchical processor models.
DAC 2003: 262-267 |
8 | EE | Gunnar Braun,
Andreas Wieferink,
Oliver Schliebusch,
Rainer Leupers,
Heinrich Meyr,
Achim Nohl:
Processor/Memory Co-Exploration on Multiple Abstraction Levels.
DATE 2003: 10966-10973 |
7 | EE | Oliver Wahlen,
Manuel Hohenauer,
Gunnar Braun,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Xiaoning Nie:
Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.
SCOPES 2003: 167-181 |
2002 |
6 | EE | Achim Nohl,
Gunnar Braun,
Oliver Schliebusch,
Rainer Leupers,
Heinrich Meyr,
Andreas Hoffmann:
A universal technique for fast and flexible instruction-set architecture simulation.
DAC 2002: 22-27 |
5 | EE | Oliver Schliebusch,
Andreas Hoffmann,
Achim Nohl,
Gunnar Braun,
Heinrich Meyr:
Architecture Implementation Using the Machine Description Language LISA.
VLSI Design 2002: 239-244 |
2001 |
4 | EE | Andreas Hoffmann,
Achim Nohl,
Stefan Pees,
Gunnar Braun,
Heinrich Meyr:
Generating production quality software development tools using a machine description language.
DATE 2001: 674-678 |
3 | EE | Andreas Hoffmann,
Oliver Schliebusch,
Achim Nohl,
Gunnar Braun,
Oliver Wahlen,
Heinrich Meyr:
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA.
ICCAD 2001: 625-630 |
2 | | Gunnar Braun,
Andreas Hoffmann,
Achim Nohl,
Heinrich Meyr:
Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description.
ISSS 2001: 57-62 |
1 | EE | Andreas Hoffmann,
Tim Kogel,
Achim Nohl,
Gunnar Braun,
Oliver Schliebusch,
Oliver Wahlen,
Andreas Wieferink,
Heinrich Meyr:
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1338-1354 (2001) |