S. K. Nandy

Soumitra Kumar Nandy

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63EEMythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan: Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC 2009: 204-215
62EEMythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan: Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP 2008: 13-18
61EEJoseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan: RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP 2008: 251-256
60EERao Adrsha, Mythri Alle, S. K. Nandy, Ranjani Narayan: Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. ASAP 2008: 287-292
59EERitesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy: Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. ASAP 2008: 49-54
58EESubhasis Banerjee, G. Surendra, S. K. Nandy: On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. Journal of Systems Architecture - Embedded Systems Design 54(8): 797-815 (2008)
57EESubhasis Banerjee, G. Surendra, S. K. Nandy: Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. ASP-DAC 2007: 884-889
56EEA. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. FPL 2007: 558-561
55EEArasu T. Senthil, C. P. Ravikumar, S. K. Nandy: Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electronics 3(1): 106-118 (2007)
54EEK. Kalapriya, S. K. Nandy, Nanjangud C. Narendra: A Framework for Measurement of End-To-End Qos Requirements in Loosely Coupled Systems. AINA (2) 2006: 926
53EESandeep B. Singh, Jayanta Biswas, S. K. Nandy: A Cost Effective Pipelined Divider for Double Precision Floating Point Number. ASAP 2006: 132-137
52EEMythri Alle, Jayanta Biswas, S. K. Nandy: High Performance VLSI Architecture Design for H.264 CAVLC Decoder. ASAP 2006: 317-322
51EEK. Kalapriya, S. K. Nandy: On the Implementation of a Streaming Video over Peer to Peer network using Middleware Components. ICN/ICONS/MCL 2006: 59
50EERaghu Anantharangachar, Gorur N. Shrinivas, S. K. Nandy: Towards Self-Composing, Prioritized and Consequential Services. IEEE SCC 2006: 518
49EEJ. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan: Framework for Enabling Highly Available Distributed Applications for Utility Computing. ISPA 2006: 549-560
48EEKeshavan Varadarajan, S. K. Nandy, Vishal Sharda, Amrutur Bharadwaj, Ravi R. Iyer, Srihari Makineni, Donald Newell: Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. MICRO 2006: 433-442
47EEG. Surendra, Subhasis Banerjee, S. K. Nandy: Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. J. Embedded Computing 2(1): 15-34 (2006)
46EEK. Kalapriya, S. K. Nandy: Throughput Driven, Highly Available Streaming Stored Playback Video Service over a Peer-to-Peer Network. AINA 2005: 229-234
45EEK. C. Nainwal, J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan: A Framework for QoS Adaptive Grid Meta Scheduling. DEXA Workshops 2005: 292-296
44EENanjangud C. Narendra, Umesh Bellur, S. K. Nandy, K. Kalapriya: Functional and architectural adaptation in pervasive computing environments. MPAC 2005: 1-7
43EEK. Kalapriya, S. K. Nandy, K. Venkatesh Babu: Can Streaming Of Stored Playback Video Be Supported On Peer to Peer Infrastructure? AINA (2) 2004: 200-203
42EEG. Surendra, Subhasis Banerjee, S. K. Nandy: Power-performance trade-off using pipeline delays. ASP-DAC 2004: 384-386
41EESubhasis Banerjee, G. Surendra, S. K. Nandy: Exploiting program execution phases to trade power and performance for media workload. ASP-DAC 2004: 387-389
40EEK. Kalapriya, S. K. Nandy, Deepti Srinivasan, R. Uma Maheshwari, V. Satish: A framework for resource discovery in pervasive computing for mobile aware task execution. Conf. Computing Frontiers 2004: 70-77
39EEK. Kalapriya, S. K. Nandy, V. Satish, R. Uma Maheshwari, Deepti Srinivas: An Architectural View of the Entities Required for Execution of Task in Pervasive Space. FTDCS 2004: 37-43
38EEG. Surendra, Subhasis Banerjee, S. K. Nandy: On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. WMPI 2004: 88-95
37EEH. Sarojadevi, S. K. Nandy, S. Balakrishnan: On the Correctness of Program Execution When Cache Coherence Is Maintained Locally at Data-Sharing Boundaries in Distributed Shared Memory Multiprocessors. International Journal of Parallel Programming 32(5): 415-446 (2004)
36EEH. Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran: Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. Asia-Pacific Computer Systems Architecture Conference 2003: 166-179
35EESatya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy: A complexity effective communication model for behavioral modeling of signal processing applications. DAC 2003: 412-415
34EEG. Surendra, Subhasis Banerjee, S. K. Nandy: Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. DATE 2003: 10784-10789
33EEAmitabh Menon, S. K. Nandy, Mahesh Mehendale: Multivoltage scheduling with voltage-partitioned variable storage. ISLPED 2003: 298-301
32 K. Kalapriya, B. R. Raghucharan, Abhijit M. Lele, S. K. Nandy: Traffic Profiling for Efficient Network Resource Utilization. International Conference on Internet Computing 2003: 789-795
31EEG. Surendra, Subhasis Banerjee, S. K. Nandy: On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. International Journal of Parallel Programming 31(6): 469-487 (2003)
30EEH. Sarojadevi, S. K. Nandy, S. Balakrishnan: Enforcing Cache Coherence at Data Sharing Boundaries without Global Control: A Hardware-Software Approach (Research Note). Euro-Par 2002: 543-546
29EEManvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishnan: Speculative Trace Scheduling in VLIW Processors. ICCD 2002: 408-413
28 Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishnan: On the Benefits of Speculative Trace Scheduling in VLIW Processors. PDPTA 2002: 822-828
27EEA. Ahmed, S. K. Nandy, Paul Sathya: Content adaptive motion estimation for mobile video encoders. ISCAS (2) 2001: 237-240
26EEAbhijit M. Lele, S. K. Nandy: Architecture of Reconfigurable a Low Power Gigabit AT Switch. VLSI Design 2001: 242-247
25EEG. Surendra, S. K. Nandy, Paul Sathya: ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. VLSI Design 2001: 85-90
24EEM. Srikanth Rao, S. K. Nandy: Power minimization using control generated clocks. DAC 2000: 794-799
23 Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema: Design Space Exploration for Orividing QoS Within the Harmony Framework. IEEE International Conference on Multimedia and Expo (I) 2000: 521-524
22 Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema: Harmony - An Architecture for Providing Quality of Service in Mobile Computing Environments. Journal of Interconnection Networks 1(3): 247-266 (2000)
21EES. Ramanathan, S. K. Nandy, V. Visvanathan: Reconfigurable Filter Coprocessor Architecture for DSP Applications. VLSI Signal Processing 26(3): 333-359 (2000)
20 Abhijit M. Lele, S. K. Nandy: Harmony - A Framework for Providing Quality of Service in Wireless Mobile Computing Environment. HiPC 1999: 299-308
19EEAvinash K. Gautam, V. Visvanathan, S. K. Nandy: Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ICCD 1999: 285-288
18EES. Ramanathan, V. Visvanathan, S. K. Nandy: Synthesis of Configurable Architectures for DSP Algorithms. VLSI Design 1999: 350-357
17EES. Ramanathan, V. Visvanathan, S. K. Nandy: Synthesis of ASIPs for DSP algorithms. Integration 28(1): 13-32 (1999)
16EES. Ramanathan, V. Visvanathan, S. K. Nandy: Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. VLSI Signal Processing 22(3): 173-195 (1999)
15EES. Balakrishnan, Soumitra Kumar Nandy: Arbitrary Precision Arithmetic - SIMD Style. VLSI Design 1998: 128-132
14EEM. R. Karthikeyan, Soumitra Kumar Nandy: An asynchronous architecture for digital signal processors. ED&TC 1997: 615
13EEVinod Menezes, S. K. Nandy, Biswadip Mitra: Signal compression through spatial frequency-based motion estimation. Integration 22(1-2): 115-135 (1997)
12EEDebabrata Ghosh, Soumitra Kumar Nandy: Wave pipelined architecture folding: a method to achieve low power and low area. VLSI Design 1995: 184-
11EEDebabrata Ghosh, S. K. Nandy: Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. IEEE Trans. VLSI Syst. 3(1): 36-48 (1995)
10 G. N. Rathna, S. K. Nandy, K. Parthasarathy: A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. VLSI Design 1994: 225-228
9 A. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal: High Speed Digital Filtering on SRAM-Based FPGAs. VLSI Design 1994: 229-232
8 Debabrata Ghosh, S. K. Nandy, K. Parthasarathy: TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. VLSI Design 1994: 77-82
7 Debabrata Ghosh, Shamik Sural, S. K. Nandy: A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. VLSI Design 1994: 95-100
6EEDebabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy: Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. DAC 1993: 303-307
5 Debabrata Ghosh, S. K. Nandy: A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. ICCD 1993: 198-201
4 S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan: A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. ICPP 1993: 94-97
3 Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan: NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. VLSI Design 1993: 341-346
2EENarasimha B. Bhat, S. K. Nandy: Special Purpose Architecture for Accelerating Bitmap DRC. DAC 1989: 674-677
1EES. K. Nandy, L. V. Ramakrishnan: Dual quadtree representation for VLSI designs. DAC 1986: 663-666

Coauthor Index

1Rao Adrsha [60]
2Manvi Agarwal [28] [29]
3A. Ahmed [27]
4Mythri Alle [52] [56] [60] [61] [62] [63]
5Raghu Anantharangachar [50]
6K. Venkatesh Babu [43]
7S. Balakrishnan [15] [28] [29] [30] [37]
8Subhasis Banerjee [31] [34] [38] [41] [42] [47] [57] [58]
9Umesh Bellur [44]
10Amrutur Bharadwaj [48]
11Narasimha B. Bhat [2]
12Jayanta Biswas [52] [53]
13Prashant S. Chauhan [4]
14Jos T. J. van Eijndhoven [28] [29]
15Dick H. J. Epema [22] [23]
16Alexander Fell [61] [62] [63]
17Ganesh Garga [59]
18Avinash K. Gautam [19]
19Debabrata Ghosh [3] [5] [6] [7] [8] [11] [12]
20S. K. Ghoshal [9]
21A. Giri [9]
22Ravi R. Iyer (Ravishankar R. Iyer) [48]
23H. S. Jamadagni [59]
24M. N. Jayram [35]
25K. Kalapriya [32] [39] [40] [43] [44] [46] [51] [54]
26M. R. Karthikeyan [14]
27M. N. V. Satya Kiran [36]
28Satya Kiran [35]
29J. Lakshmi [45] [49]
30Abhijit M. Lele [20] [22] [23] [26] [32]
31R. Uma Maheshwari [39] [40]
32Srihari Makineni [48]
33Mahesh Mehendale [33]
34Vinod Menezes [13]
35Amitabh Menon [33]
36Biswadip Mitra [13]
37K. C. Nainwal [45]
38Ranjani Narayan [4] [45] [49] [56] [60] [61] [62] [63]
39Nanjangud C. Narendra [44] [54]
40Donald Newell [48]
41Joseph Nimmy [61] [62]
42K. Parthasarathy [3] [6] [8] [10]
43B. R. Raghucharan [32]
44Ritesh Rajore [59]
45L. V. Ramakrishnan [1]
46S. Ramanathan [16] [17] [18] [21]
47Ramesh C. Ramesh [62]
48Adarsha Rao [62]
49H. Pradeep Rao [36]
50M. Srikanth Rao [24]
51Pradeep Rao [35]
52G. N. Rathna [10]
53C. P. Ravikumar [55]
54C. Ramesh Reddy [61]
55P. Sadayappan [4] [6]
56H. Sarojadevi [30] [37]
57Paul Sathya [25] [27]
58V. Satish [39] [40]
59A. N. Satrawala [56]
60Arasu T. Senthil [55]
61Vishal Sharda [48]
62Gorur N. Shrinivas [50]
63Sandeep B. Singh [53]
64Deepti Srinivas [39]
65Deepti Srinivasan [40]
66Shamik Sural [7]
67G. Surendra [25] [31] [34] [38] [41] [42] [47] [57] [58]
68Keshavan Varadarajan [45] [48] [49] [56] [61] [62] [63]
69V. Visvanathan [3] [4] [9] [16] [17] [18] [19] [21]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)