S. K. Nandy

Soumitra Kumar Nandy

2009
63	EE	Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan: Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC 2009: 204-215
2008
62	EE	Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan: Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP 2008: 13-18
61	EE	Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan: RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP 2008: 251-256
60	EE	Rao Adrsha, Mythri Alle, S. K. Nandy, Ranjani Narayan: Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. ASAP 2008: 287-292
59	EE	Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy: Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. ASAP 2008: 49-54
58	EE	Subhasis Banerjee, G. Surendra, S. K. Nandy: On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. Journal of Systems Architecture - Embedded Systems Design 54(8): 797-815 (2008)
2007
57	EE	Subhasis Banerjee, G. Surendra, S. K. Nandy: Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. ASP-DAC 2007: 884-889
56	EE	A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. FPL 2007: 558-561
55	EE	Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy: Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electronics 3(1): 106-118 (2007)
2006
54	EE	K. Kalapriya, S. K. Nandy, Nanjangud C. Narendra: A Framework for Measurement of End-To-End Qos Requirements in Loosely Coupled Systems. AINA (2) 2006: 926
53	EE	Sandeep B. Singh, Jayanta Biswas, S. K. Nandy: A Cost Effective Pipelined Divider for Double Precision Floating Point Number. ASAP 2006: 132-137
52	EE	Mythri Alle, Jayanta Biswas, S. K. Nandy: High Performance VLSI Architecture Design for H.264 CAVLC Decoder. ASAP 2006: 317-322
51	EE	K. Kalapriya, S. K. Nandy: On the Implementation of a Streaming Video over Peer to Peer network using Middleware Components. ICN/ICONS/MCL 2006: 59
50	EE	Raghu Anantharangachar, Gorur N. Shrinivas, S. K. Nandy: Towards Self-Composing, Prioritized and Consequential Services. IEEE SCC 2006: 518
49	EE	J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan: Framework for Enabling Highly Available Distributed Applications for Utility Computing. ISPA 2006: 549-560
48	EE	Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Amrutur Bharadwaj, Ravi R. Iyer, Srihari Makineni, Donald Newell: Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. MICRO 2006: 433-442
47	EE	G. Surendra, Subhasis Banerjee, S. K. Nandy: Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. J. Embedded Computing 2(1): 15-34 (2006)
2005
46	EE	K. Kalapriya, S. K. Nandy: Throughput Driven, Highly Available Streaming Stored Playback Video Service over a Peer-to-Peer Network. AINA 2005: 229-234
45	EE	K. C. Nainwal, J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan: A Framework for QoS Adaptive Grid Meta Scheduling. DEXA Workshops 2005: 292-296
44	EE	Nanjangud C. Narendra, Umesh Bellur, S. K. Nandy, K. Kalapriya: Functional and architectural adaptation in pervasive computing environments. MPAC 2005: 1-7
2004
43	EE	K. Kalapriya, S. K. Nandy, K. Venkatesh Babu: Can Streaming Of Stored Playback Video Be Supported On Peer to Peer Infrastructure? AINA (2) 2004: 200-203
42	EE	G. Surendra, Subhasis Banerjee, S. K. Nandy: Power-performance trade-off using pipeline delays. ASP-DAC 2004: 384-386
41	EE	Subhasis Banerjee, G. Surendra, S. K. Nandy: Exploiting program execution phases to trade power and performance for media workload. ASP-DAC 2004: 387-389
40	EE	K. Kalapriya, S. K. Nandy, Deepti Srinivasan, R. Uma Maheshwari, V. Satish: A framework for resource discovery in pervasive computing for mobile aware task execution. Conf. Computing Frontiers 2004: 70-77
39	EE	K. Kalapriya, S. K. Nandy, V. Satish, R. Uma Maheshwari, Deepti Srinivas: An Architectural View of the Entities Required for Execution of Task in Pervasive Space. FTDCS 2004: 37-43
38	EE	G. Surendra, Subhasis Banerjee, S. K. Nandy: On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. WMPI 2004: 88-95
37	EE	H. Sarojadevi, S. K. Nandy, S. Balakrishnan: On the Correctness of Program Execution When Cache Coherence Is Maintained Locally at Data-Sharing Boundaries in Distributed Shared Memory Multiprocessors. International Journal of Parallel Programming 32(5): 415-446 (2004)
2003
36	EE	H. Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran: Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. Asia-Pacific Computer Systems Architecture Conference 2003: 166-179
35	EE	Satya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy: A complexity effective communication model for behavioral modeling of signal processing applications. DAC 2003: 412-415
34	EE	G. Surendra, Subhasis Banerjee, S. K. Nandy: Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. DATE 2003: 10784-10789
33	EE	Amitabh Menon, S. K. Nandy, Mahesh Mehendale: Multivoltage scheduling with voltage-partitioned variable storage. ISLPED 2003: 298-301
32		K. Kalapriya, B. R. Raghucharan, Abhijit M. Lele, S. K. Nandy: Traffic Profiling for Efficient Network Resource Utilization. International Conference on Internet Computing 2003: 789-795
31	EE	G. Surendra, Subhasis Banerjee, S. K. Nandy: On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. International Journal of Parallel Programming 31(6): 469-487 (2003)
2002
30	EE	H. Sarojadevi, S. K. Nandy, S. Balakrishnan: Enforcing Cache Coherence at Data Sharing Boundaries without Global Control: A Hardware-Software Approach (Research Note). Euro-Par 2002: 543-546
29	EE	Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishnan: Speculative Trace Scheduling in VLIW Processors. ICCD 2002: 408-413
28		Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishnan: On the Benefits of Speculative Trace Scheduling in VLIW Processors. PDPTA 2002: 822-828
2001
27	EE	A. Ahmed, S. K. Nandy, Paul Sathya: Content adaptive motion estimation for mobile video encoders. ISCAS (2) 2001: 237-240
26	EE	Abhijit M. Lele, S. K. Nandy: Architecture of Reconfigurable a Low Power Gigabit AT Switch. VLSI Design 2001: 242-247
25	EE	G. Surendra, S. K. Nandy, Paul Sathya: ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. VLSI Design 2001: 85-90
2000
24	EE	M. Srikanth Rao, S. K. Nandy: Power minimization using control generated clocks. DAC 2000: 794-799
23		Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema: Design Space Exploration for Orividing QoS Within the Harmony Framework. IEEE International Conference on Multimedia and Expo (I) 2000: 521-524
22		Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema: Harmony - An Architecture for Providing Quality of Service in Mobile Computing Environments. Journal of Interconnection Networks 1(3): 247-266 (2000)
21	EE	S. Ramanathan, S. K. Nandy, V. Visvanathan: Reconfigurable Filter Coprocessor Architecture for DSP Applications. VLSI Signal Processing 26(3): 333-359 (2000)
1999
20		Abhijit M. Lele, S. K. Nandy: Harmony - A Framework for Providing Quality of Service in Wireless Mobile Computing Environment. HiPC 1999: 299-308
19	EE	Avinash K. Gautam, V. Visvanathan, S. K. Nandy: Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ICCD 1999: 285-288
18	EE	S. Ramanathan, V. Visvanathan, S. K. Nandy: Synthesis of Configurable Architectures for DSP Algorithms. VLSI Design 1999: 350-357
17	EE	S. Ramanathan, V. Visvanathan, S. K. Nandy: Synthesis of ASIPs for DSP algorithms. Integration 28(1): 13-32 (1999)
16	EE	S. Ramanathan, V. Visvanathan, S. K. Nandy: Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. VLSI Signal Processing 22(3): 173-195 (1999)
1998
15	EE	S. Balakrishnan, Soumitra Kumar Nandy: Arbitrary Precision Arithmetic - SIMD Style. VLSI Design 1998: 128-132
1997
14	EE	M. R. Karthikeyan, Soumitra Kumar Nandy: An asynchronous architecture for digital signal processors. ED&TC 1997: 615
13	EE	Vinod Menezes, S. K. Nandy, Biswadip Mitra: Signal compression through spatial frequency-based motion estimation. Integration 22(1-2): 115-135 (1997)
1995
12	EE	Debabrata Ghosh, Soumitra Kumar Nandy: Wave pipelined architecture folding: a method to achieve low power and low area. VLSI Design 1995: 184-
11	EE	Debabrata Ghosh, S. K. Nandy: Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. IEEE Trans. VLSI Syst. 3(1): 36-48 (1995)
1994
10		G. N. Rathna, S. K. Nandy, K. Parthasarathy: A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. VLSI Design 1994: 225-228
9		A. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal: High Speed Digital Filtering on SRAM-Based FPGAs. VLSI Design 1994: 229-232
8		Debabrata Ghosh, S. K. Nandy, K. Parthasarathy: TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. VLSI Design 1994: 77-82
7		Debabrata Ghosh, Shamik Sural, S. K. Nandy: A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. VLSI Design 1994: 95-100
1993
6	EE	Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy: Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. DAC 1993: 303-307
5		Debabrata Ghosh, S. K. Nandy: A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. ICCD 1993: 198-201
4		S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan: A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. ICPP 1993: 94-97
3		Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan: NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. VLSI Design 1993: 341-346
1989
2	EE	Narasimha B. Bhat, S. K. Nandy: Special Purpose Architecture for Accelerating Bitmap DRC. DAC 1989: 674-677
1986
1	EE	S. K. Nandy, L. V. Ramakrishnan: Dual quadtree representation for VLSI designs. DAC 1986: 663-666

Coauthor Index

1	Rao Adrsha	[60]
2	Manvi Agarwal	[28] [29]
3	A. Ahmed	[27]
4	Mythri Alle	[52] [56] [60] [61] [62] [63]
5	Raghu Anantharangachar	[50]
6	K. Venkatesh Babu	[43]
7	S. Balakrishnan	[15] [28] [29] [30] [37]
8	Subhasis Banerjee	[31] [34] [38] [41] [42] [47] [57] [58]
9	Umesh Bellur	[44]
10	Amrutur Bharadwaj	[48]
11	Narasimha B. Bhat	[2]
12	Jayanta Biswas	[52] [53]
13	Prashant S. Chauhan	[4]
14	Jos T. J. van Eijndhoven	[28] [29]
15	Dick H. J. Epema	[22] [23]
16	Alexander Fell	[61] [62] [63]
17	Ganesh Garga	[59]
18	Avinash K. Gautam	[19]
19	Debabrata Ghosh	[3] [5] [6] [7] [8] [11] [12]
20	S. K. Ghoshal	[9]
21	A. Giri	[9]
22	Ravi R. Iyer (Ravishankar R. Iyer)	[48]
23	H. S. Jamadagni	[59]
24	M. N. Jayram	[35]
25	K. Kalapriya	[32] [39] [40] [43] [44] [46] [51] [54]
26	M. R. Karthikeyan	[14]
27	M. N. V. Satya Kiran	[36]
28	Satya Kiran	[35]
29	J. Lakshmi	[45] [49]
30	Abhijit M. Lele	[20] [22] [23] [26] [32]
31	R. Uma Maheshwari	[39] [40]
32	Srihari Makineni	[48]
33	Mahesh Mehendale	[33]
34	Vinod Menezes	[13]
35	Amitabh Menon	[33]
36	Biswadip Mitra	[13]
37	K. C. Nainwal	[45]
38	Ranjani Narayan	[4] [45] [49] [56] [60] [61] [62] [63]
39	Nanjangud C. Narendra	[44] [54]
40	Donald Newell	[48]
41	Joseph Nimmy	[61] [62]
42	K. Parthasarathy	[3] [6] [8] [10]
43	B. R. Raghucharan	[32]
44	Ritesh Rajore	[59]
45	L. V. Ramakrishnan	[1]
46	S. Ramanathan	[16] [17] [18] [21]
47	Ramesh C. Ramesh	[62]
48	Adarsha Rao	[62]
49	H. Pradeep Rao	[36]
50	M. Srikanth Rao	[24]
51	Pradeep Rao	[35]
52	G. N. Rathna	[10]
53	C. P. Ravikumar	[55]
54	C. Ramesh Reddy	[61]
55	P. Sadayappan	[4] [6]
56	H. Sarojadevi	[30] [37]
57	Paul Sathya	[25] [27]
58	V. Satish	[39] [40]
59	A. N. Satrawala	[56]
60	Arasu T. Senthil	[55]
61	Vishal Sharda	[48]
62	Gorur N. Shrinivas	[50]
63	Sandeep B. Singh	[53]
64	Deepti Srinivas	[39]
65	Deepti Srinivasan	[40]
66	Shamik Sural	[7]
67	G. Surendra	[25] [31] [34] [38] [41] [42] [47] [57] [58]
68	Keshavan Varadarajan	[45] [48] [49] [56] [61] [62] [63]
69	V. Visvanathan	[3] [4] [9] [16] [17] [18] [19] [21]

Colors in the list of coauthors