| 2006 |
|---|
| 9 | EE | Yu-Chin Hsu,
Fur-Shing Tsai,
Wells Jong,
Ying-Tsai Chang:
Visibility enhancement for silicon debug.
DAC 2006: 13-18 |
| 2003 |
|---|
| 8 | EE | Yu-Chin Hsu,
Bassam Tabbara,
Yirng-An Chen,
Fur-Shing Tsai:
Advanced techniques for RTL debugging.
DAC 2003: 362-367 |
| 2002 |
|---|
| 7 | EE | Shi-Zheng Eric Lin,
Chieh Changfan,
Yu-Chin Hsu,
Fur-Shing Tsai:
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.
ACM Trans. Design Autom. Electr. Syst. 7(1): 217-230 (2002) |
| 2000 |
|---|
| 6 | EE | Chieh Changfan,
Yu-Chin Hsu,
Fur-Shing Tsai:
Timing optimization on routed designs with incremental placementand routing characterization.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 188-196 (2000) |
| 1999 |
|---|
| 5 | EE | Chieh Changfan,
Yu-Chin Hsu,
Fur-Shing Tsai:
Post-routing timing optimization with routing characterization.
ISPD 1999: 30-35 |
| 1992 |
|---|
| 4 | EE | Fur-Shing Tsai,
Yu-Chin Hsu:
STAR: An automatic data path allocator.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1053-1064 (1992) |
| 1990 |
|---|
| 3 | | Fur-Shing Tsai,
Yu-Chin Hsu:
Data Path Construction and Refinement.
ICCAD 1990: 308-311 |
| 2 | EE | Youn-Long Lin,
Yu-Chin Hsu,
Fur-Shing Tsai:
Hybrid routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 151-157 (1990) |
| 1989 |
|---|
| 1 | EE | Youn-Long Lin,
Yu-Chin Hsu,
Fur-Shing Tsai:
SILK: a simulated evolution router.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1108-1114 (1989) |
