2008 |
17 | EE | George Kornaros,
Wolfram Lautenschlaeger,
Matthias Sund,
Helen-Catherine Leligou:
Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching.
FPL 2008: 639-642 |
2007 |
16 | EE | Ioannis Papaefstathiou,
George Kornaros,
Nikolaos Chrysos:
A buffered crossbar-based chip interconnection framework supporting quality of service.
ACM Great Lakes Symposium on VLSI 2007: 90-95 |
15 | EE | Theofanis Orphanoudakis,
George Kornaros,
Ioannis Mavroidis,
Aristides Nikologiannis,
Ioannis Papaefstathiou:
An Embedded Networking SoC for purely Ethernet MANs/WANs.
ISCC 2007: 901-906 |
14 | EE | Ioannis Papaefstathiou,
Theofanis Orphanoudakis,
George Kornaros,
Christopher Kachris,
Ioannis Mavroidis,
Aristides Nikologiannis:
Queue Management in Network Processors
CoRR abs/0710.4813: (2007) |
2006 |
13 | EE | George Kornaros:
BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory.
DSD 2006: 180-188 |
2005 |
12 | EE | Ioannis Papaefstathiou,
Theofanis Orphanoudakis,
George Kornaros,
Christopher Kachris,
Ioannis Mavroidis,
Aristides Nikologiannis:
Queue Management in Network Processors.
DATE 2005: 112-117 |
2004 |
11 | EE | Ioannis Papaefstathiou,
George Kornaros,
Nicholaos Zervos:
Software Processing Performance in Network Processors.
DATE 2004: 186-191 |
10 | EE | Ioannis Papaefstathiou,
Stylianos Perissakis,
Theofanis Orphanoudakis,
Nikos A. Nikolaou,
George Kornaros,
Nicholas Zervos,
George E. Konstantoulakis,
Dionisios N. Pnevmatikatos,
Kyriakos Vlachos:
PRO3: A Hybrid NPU Architecture.
IEEE Micro 24(5): 20-33 (2004) |
9 | EE | Aristides Nikologiannis,
Ioannis Papaefstathiou,
George Kornaros,
Christopher Kachris:
An FPGA-based queue management system for high speed networking devices.
Microprocessors and Microsystems 28(5-6): 223-236 (2004) |
2003 |
8 | EE | George Kornaros,
Theofanis Orphanoudakis,
Ioannis Papaefstathiou:
GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks.
ASAP 2003: 389-399 |
7 | EE | George Kornaros,
Ioannis Papaefstathiou,
Aristides Nikologiannis,
Nicholaos Zervos:
A fully-programmable memory management system optimizing queue handling at multi-gigabit rates.
DAC 2003: 54-59 |
6 | EE | George Kornaros,
Theofanis Orphanoudakis,
Nicholaos Zervos:
An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures.
DSD 2003: 197-205 |
5 | EE | George Kornaros,
Ioannis Papaefstathiou:
An Innovative Resource Management Scheme for Multi-gigabit Networking Systems.
HSNMC 2003: 165-175 |
4 | EE | Ioannis Papaefstathiou,
Helen-Catherine Leligou,
Theofanis Orphanoudakis,
George Kornaros,
Nicholaos Zervos,
George E. Konstantoulakis:
An innovative scheduling scheme for high-speed network processors.
ISCAS (2) 2003: 93-96 |
3 | EE | George Kornaros,
Theofanis Orphanoudakis,
Ioannis Papaefstathiou:
Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors.
ISCAS (2) 2003: 97-100 |
2 | EE | Kyriakos Vlachos,
Nikos A. Nikolaou,
Theofanis Orphanoudakis,
Stylianos Perissakis,
Dionisios N. Pnevmatikatos,
George Kornaros,
J. A. Sanchez,
George E. Konstantoulakis:
Processing and Scheduling Components in an Innovative Network Processor Architecture.
VLSI Design 2003: 195-201 |
1997 |
1 | EE | George Kornaros,
Christoforos E. Kozyrakis,
Panagiota Vatsolaki,
Manolis Katevenis:
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control.
ARVLSI 1997: 127-144 |