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George Kornaros

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2008
17EEGeorge Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine Leligou: Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching. FPL 2008: 639-642
2007
16EEIoannis Papaefstathiou, George Kornaros, Nikolaos Chrysos: A buffered crossbar-based chip interconnection framework supporting quality of service. ACM Great Lakes Symposium on VLSI 2007: 90-95
15EETheofanis Orphanoudakis, George Kornaros, Ioannis Mavroidis, Aristides Nikologiannis, Ioannis Papaefstathiou: An Embedded Networking SoC for purely Ethernet MANs/WANs. ISCC 2007: 901-906
14EEIoannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis: Queue Management in Network Processors CoRR abs/0710.4813: (2007)
2006
13EEGeorge Kornaros: BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory. DSD 2006: 180-188
2005
12EEIoannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis: Queue Management in Network Processors. DATE 2005: 112-117
2004
11EEIoannis Papaefstathiou, George Kornaros, Nicholaos Zervos: Software Processing Performance in Network Processors. DATE 2004: 186-191
10EEIoannis Papaefstathiou, Stylianos Perissakis, Theofanis Orphanoudakis, Nikos A. Nikolaou, George Kornaros, Nicholas Zervos, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Kyriakos Vlachos: PRO3: A Hybrid NPU Architecture. IEEE Micro 24(5): 20-33 (2004)
9EEAristides Nikologiannis, Ioannis Papaefstathiou, George Kornaros, Christopher Kachris: An FPGA-based queue management system for high speed networking devices. Microprocessors and Microsystems 28(5-6): 223-236 (2004)
2003
8EEGeorge Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou: GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks. ASAP 2003: 389-399
7EEGeorge Kornaros, Ioannis Papaefstathiou, Aristides Nikologiannis, Nicholaos Zervos: A fully-programmable memory management system optimizing queue handling at multi-gigabit rates. DAC 2003: 54-59
6EEGeorge Kornaros, Theofanis Orphanoudakis, Nicholaos Zervos: An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures. DSD 2003: 197-205
5EEGeorge Kornaros, Ioannis Papaefstathiou: An Innovative Resource Management Scheme for Multi-gigabit Networking Systems. HSNMC 2003: 165-175
4EEIoannis Papaefstathiou, Helen-Catherine Leligou, Theofanis Orphanoudakis, George Kornaros, Nicholaos Zervos, George E. Konstantoulakis: An innovative scheduling scheme for high-speed network processors. ISCAS (2) 2003: 93-96
3EEGeorge Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou: Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors. ISCAS (2) 2003: 97-100
2EEKyriakos Vlachos, Nikos A. Nikolaou, Theofanis Orphanoudakis, Stylianos Perissakis, Dionisios N. Pnevmatikatos, George Kornaros, J. A. Sanchez, George E. Konstantoulakis: Processing and Scheduling Components in an Innovative Network Processor Architecture. VLSI Design 2003: 195-201
1997
1EEGeorge Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis: Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. ARVLSI 1997: 127-144

Coauthor Index

1Nikolaos Chrysos [16]
2Christoforos Kachris (Christopher Kachris) [9] [12] [14]
3Manolis Katevenis [1]
4George E. Konstantoulakis [2] [4] [10]
5Christoforos E. Kozyrakis (Christos Kozyrakis) [1]
6Wolfram Lautenschlaeger [17]
7Helen-Catherine Leligou [4] [17]
8Ioannis Mavroidis [12] [14] [15]
9Nikos A. Nikolaou [2] [10]
10Aristides Nikologiannis [7] [9] [12] [14] [15]
11Theofanis Orphanoudakis [2] [3] [4] [6] [8] [10] [12] [14] [15]
12Ioannis Papaefstathiou [3] [4] [5] [7] [8] [9] [10] [11] [12] [14] [15] [16]
13Stylianos Perissakis [2] [10]
14Dionisios N. Pnevmatikatos [2] [10]
15J. A. Sanchez [2]
16Matthias Sund [17]
17Panagiota Vatsolaki [1]
18Kyriakos Vlachos [2] [10]
19Nicholaos Zervos (Nicholas Zervos) [4] [6] [7] [10] [11]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)