2006 |
11 | EE | Usha Narasimha,
Anthony M. Hill,
N. S. Nagaraj:
SmartExtract: Accurate Capacitance Extraction for SOC Designs.
VLSI Design 2006: 786-789 |
2005 |
10 | EE | N. S. Nagaraj,
Tom Bonifield,
Abha Singh,
Clive Bittlestone,
Usha Narasimha,
Viet Le,
Anthony M. Hill:
BEOL variability and impact on RC extraction.
DAC 2005: 758-759 |
2004 |
9 | EE | Sanjive Agarwala,
Paul Wiley,
Arjun Rajagopal,
Anthony M. Hill,
Raguram Damodaran,
Lewis Nardini,
Tim Anderson,
Steven Mullinnix,
Jose Flores,
Heping Yue,
Abhijeet Chachad,
John Apostol,
Kyle Castille,
Usha Narasimha,
Tod Wolf,
N. S. Nagaraj,
Manjeri Krishnan,
Luong Nguyen,
Todd Kroeger,
Mike Gill,
Peter Groves,
Bill Webster,
Joel Graber,
Christine Karlovich:
A 800 MHz System-on-Chip for Wireless Infrastructure Applications.
VLSI Design 2004: 381- |
2003 |
8 | EE | Clive Bittlestone,
Anthony M. Hill,
Vipul Singhal,
N. V. Arvind:
Architecting ASIC libraries and flows in nanometer era.
DAC 2003: 776-781 |
2002 |
7 | EE | Robert W. Brodersen,
Anthony M. Hill,
John Kibarian,
Desmond Kirkpatrick,
Mark A. Lavin,
Mitsumasa Koyanagi:
Nanometer design: what hurts next...?
DAC 2002: 242 |
1997 |
6 | EE | Uming Ko,
Andrew Pua,
Anthony M. Hill,
Pranjal Srivastava:
Hybrid dual-threshold design techniques for high-performance processors with low-power features.
ISLPED 1997: 307-311 |
1996 |
5 | EE | Uming Ko,
Anthony M. Hill,
Poras T. Balsara:
Design techniques for high performance, energy efficient control logic.
ISLPED 1996: 97-100 |
4 | EE | Anthony M. Hill,
Sung-Mo Kang:
Determining accuracy bounds for simulation-based switching activity estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 611-618 (1996) |
1995 |
3 | EE | Chin-Chi Teng,
Anthony M. Hill,
Sung-Mo Kang:
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.
ICCAD 1995: 366-370 |
2 | EE | Anthony M. Hill,
Sung-Mo Kang:
Determining accuracy bounds for simulation-based switching activity estimation.
ISLPD 1995: 215-220 |
1994 |
1 | | Anthony M. Hill,
Sung-Mo Kang:
Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits.
PPSN 1994: 546-555 |