2009 | ||
---|---|---|
34 | EE | Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong: Incremental power optimization for multiple supply voltage design. ISQED 2009: 280-286 |
33 | EE | Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong: Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED 2009: 740-745 |
2008 | ||
32 | EE | Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong: LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212 |
31 | EE | Jiemin Liu, Yuchun Ma, Yuan Gao: MRAPF: Minimum RTT Asymmetric-Path First for Mobile Multi-homed End-to-End Transfer. FSKD (4) 2008: 86-90 |
30 | EE | Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong: IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. ISQED 2008: 873-876 |
29 | EE | Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong: Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. JETC 4(4): (2008) |
2007 | ||
28 | EE | Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong: An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569 |
27 | EE | Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong: Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC 2007: 191-196 |
26 | EE | Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou: Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925 |
25 | EE | Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou: 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597 |
24 | EE | Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong: Fine grain 3D integration for microarchitecture design through cube packing exploration. ICCD 2007: 259-266 |
23 | EE | Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma: A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS 2007: 2044-2047 |
22 | EE | Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong: Interconnect Power Optimization Based on Timing Analysis. ISVLSI 2007: 119-124 |
21 | EE | Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma: An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP 2007: 25-32 |
2006 | ||
20 | EE | Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma: A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS 2006: 792-795 |
19 | EE | Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang: An automated design flow for 3D microarchitecture evaluation. ASP-DAC 2006: 384-389 |
18 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006) |
2005 | ||
17 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866 |
16 | EE | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225 |
15 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219 |
14 | EE | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633 |
13 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu: Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 609-621 (2005) |
2004 | ||
12 | EE | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 |
11 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 |
10 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004) |
9 | EE | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu: Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004) |
2003 | ||
8 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 |
7 | EE | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 |
6 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu: Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 |
5 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142 |
2002 | ||
4 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. VLSI Design 2002: 387-392 |
2001 | ||
3 | EE | Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu: VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514 |
2 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775 |
1 | EE | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with abutment constraints based on corner block list. Integration 31(1): 65-77 (2001) |