| 2008 |
|---|
| 20 | EE | Hong Phuc Ninh,
Takashi Moue,
Takashi Kurashina,
Kenichi Okada,
Akira Matsuzawa:
A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio.
ASP-DAC 2008: 103-104 |
| 19 | EE | Christian Jesús B. Fayomi,
Gilson I. Wirth,
Jaime Ramírez-Angulo,
Akira Matsuzawa:
"The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit.
ISCAS 2008: 1716-1719 |
| 18 | EE | Shoichi Hara,
Takeshi Ito,
Kenichi Okada,
Akira Matsuzawa:
Design space exploration of low-phase-noise LC-VCO using multiple-divide technique.
ISCAS 2008: 1966-1969 |
| 17 | EE | Masaya Miyahara,
Akira Matsuzawa:
A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing.
IEICE Transactions 91-A(2): 469-475 (2008) |
| 2007 |
|---|
| 16 | EE | Akira Matsuzawa:
Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS.
IEICE Transactions 90-C(4): 779-785 (2007) |
| 15 | EE | Win Chaivipas,
Akira Matsuzawa:
Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop.
IEICE Transactions 90-C(4): 793-801 (2007) |
| 14 | EE | Masaya Miyahara,
Akira Matsuzawa:
The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time.
IEICE Transactions 90-C(6): 1165-1171 (2007) |
| 13 | EE | Yusuke Ikeda,
Akira Matsuzawa:
Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC.
IEICE Transactions 90-C(6): 1172-1180 (2007) |
| 12 | EE | Philipus Chandra Oh,
Akira Matsuzawa,
Win Chaivipas:
A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter.
IEICE Transactions 90-C(6): 1311-1314 (2007) |
| 2006 |
|---|
| 11 | EE | Win Chaivipas,
Akira Matsuzawa,
Philipus Chandra Oh:
Feedforward compensation technique for all digital phase locked loop based synthesizers.
ISCAS 2006 |
| 10 | EE | Akira Matsuzawa:
Analog IC Technologies for Future Wireless Systems.
IEICE Transactions 89-C(4): 446-454 (2006) |
| 2003 |
|---|
| 9 | EE | Akira Matsuzawa:
How to make efficient communication, collaboration, and optimization from system to chip.
DAC 2003: 417-418 |
| 8 | | Akira Matsuzawa:
Driving the SoC developments for digital consumer electronics.
ESTImedia 2003: 5-7 |
| 2002 |
|---|
| 7 | | Dwi Handoko,
Shoji Kawahito,
Yoshiaki Tadokoro,
Akira Matsuzawa:
Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor.
IEEE Trans. Circuits Syst. Video Techn. 12(12): 1084- (2002) |
| 2001 |
|---|
| 6 | EE | Akira Matsuzawa:
High Quality Analog CMOS and Mixed Signal LSI Design.
ISQED 2001: 97-104 |
| 1998 |
|---|
| 5 | | Shoji Kawahito,
Makoto Yoshida,
Masaaki Sasaki,
Daisuke Miyazaki,
Yoshiaki Tadokoro,
Kenji Murata,
Shiro Doushou,
Akira Matsuzawa:
A CMOS Smart Image Sensor LSI for Focal-Plane Compression.
ASP-DAC 1998: 339-340 |
| 4 | | Shoji Kawahito,
Yoshiaki Tadokoro,
Akira Matsuzawa:
CMOS Image Sensors with Video Compression.
ASP-DAC 1998: 595-600 |
| 1997 |
|---|
| 3 | | Kenneth P. Parker,
John E. McDermid,
Rodney A. Browen,
Kozo Nuriya,
Katsuhiro Hirayama,
Akira Matsuzawa:
Design, Fabrications and Use of Mixed-Signal IC Testability Structures.
ITC 1997: 489-498 |
| 2 | EE | Hiroyuki Yamauchi,
Toru Iwata,
Hironori Akamatsu,
Akira Matsuzawa:
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture.
IEEE Trans. VLSI Syst. 5(4): 377-387 (1997) |
| 1996 |
|---|
| 1 | EE | Hiroyuki Yamauchi,
Toru Iwata,
Hironori Akamatsu,
Akira Matsuzawa:
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes.
ISLPED 1996: 49-54 |
