2008 |
15 | EE | Yonghyun Hwang,
Samar Abdi,
Daniel Gajski:
Cycle-approximate Retargetable Performance Estimation at the Transaction Level.
DATE 2008: 3-8 |
14 | EE | Daniel D. Gajski,
Samar Abdi,
Ines Viskic:
Model Based Synthesis of Embedded Software.
SEUS 2008: 21-33 |
2007 |
13 | EE | Lochi Lo Chi Yu Lo,
Samar Abdi:
Automatic SystemC TLM generation for custom communication platforms.
ICCD 2007: 41-46 |
12 | EE | Hansu Cho,
Samar Abdi,
Daniel Gajski:
Interface synthesis for heterogeneous multi-core systems from transaction level models.
LCTES 2007: 140-142 |
11 | EE | Ines Viskic,
Samar Abdi,
Daniel D. Gajski:
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms.
LCTES 2007: 143-145 |
2006 |
10 | EE | Hansu Cho,
Samar Abdi,
Daniel Gajski:
Design and implementation of transducer for ARM-TMS communication.
ASP-DAC 2006: 126-127 |
9 | EE | Samar Abdi,
Daniel Gajski:
Verification of System Level Model Transformations.
International Journal of Parallel Programming 34(1): 29-59 (2006) |
2005 |
8 | EE | Samar Abdi,
Daniel Gajski:
A formalism for functionality preserving system level transformations.
ASP-DAC 2005: 139-144 |
7 | EE | Junyu Peng,
Samar Abdi,
Daniel Gajski:
A clustering technique to optimize hardware/software synchronization.
ASP-DAC 2005: 965-968 |
6 | EE | Samar Abdi,
Daniel D. Gajski:
Functional Validation of System Level Static Scheduling.
DATE 2005: 542-547 |
2004 |
5 | EE | Samar Abdi,
Daniel Gajski:
On deriving equivalent architecture model from system specification.
ASP-DAC 2004: 322-327 |
4 | EE | Dongwan Shin,
Samar Abdi,
Daniel Gajski:
Automatic generation of bus functional models from transaction level models.
ASP-DAC 2004: 756-758 |
3 | EE | Samar Abdi,
Daniel Gajski:
Automatic generation of equivalent architecture model from functional specification.
DAC 2004: 608-613 |
2003 |
2 | EE | Samar Abdi,
Dongwan Shin,
Daniel Gajski:
Automatic communication refinement for system level design.
DAC 2003: 300-305 |
2002 |
1 | EE | Junyu Peng,
Samar Abdi,
Daniel Gajski:
Automatic Model Refinement for Fast Architecture Exploration.
VLSI Design 2002: 332-337 |