Takayasu Sakurai

2008
45	EE	Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai: Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators. ISLPED 2008: 117-122
44	EE	Takayasu Sakurai: Next-generation power-aware design. ISLPED 2008: 383-384
43	EE	Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai: Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. ISQED 2008: 133-136
2007
42	EE	Takayasu Sakurai: Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future". ASP-DAC 2007
41	EE	Takayasu Sakurai: Meeting with the forthcoming IC design. SBCCI 2007: 2
40	EE	Hiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai: Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines. IEICE Transactions 90-A(12): 2669-2681 (2007)
39	EE	Fayez Robert Saliba, Hiroshi Kawaguchi, Takayasu Sakurai: A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's. IEICE Transactions 90-C(4): 743-748 (2007)
38	EE	Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai: An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors. IEICE Transactions 90-C(4): 786-792 (2007)
37	EE	Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda: Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Transactions 90-C(4): 829-835 (2007)
2006
36	EE	Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai: A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. ASP-DAC 2006: 98-99
35	EE	Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai: Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs. IEEE Trans. VLSI Syst. 14(4): 430-435 (2006)
34	EE	Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai: Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's. IEICE Transactions 89-A(12): 3569-3578 (2006)
33	EE	Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai: Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping. IEICE Transactions 89-C(3): 280-286 (2006)
32	EE	Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda: A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. IEICE Transactions 89-C(3): 320-326 (2006)
31	EE	Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai: Trends of On-Chip Interconnects in Deep Sub-Micron VLSI. IEICE Transactions 89-C(3): 392-394 (2006)
2005
30	EE	Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai: More than two orders of magnitude leakage current reduction in look-up table for FPGAs. ISCAS (5) 2005: 4701-4704
29	EE	Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai: /spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. IEEE Transactions on Multimedia 7(1): 67-74 (2005)
28	EE	Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai: Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. IEICE Transactions 88-C(4): 760-767 (2005)
27	EE	Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai: Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Systems and Computers in Japan 36(6): 39-48 (2005)
2003
26	EE	Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15
2002
25	EE	Takayasu Sakurai: Minimizing power across multiple technology and design levels. ICCAD 2002: 24-27
24	EE	Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai: CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. ISCAS (5) 2002: 545-548
23	EE	Koichi Nose, Takayasu Sakurai: Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. ISLPED 2002: 24-29
22	EE	Takayasu Sakurai: Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited). ISQED 2002: 445-450
21	EE	Seongsoo Lee, Seungjun Lee, Takayasu Sakurai: Energy-Constrained VDD Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems. Journal of Circuits, Systems, and Computers 11(6): 601-620 (2002)
2001
20	EE	Youngsoo Shin, Takayasu Sakurai: Coupling-Driven Bus Design for Low-Power Application-Specific Systems. DAC 2001: 750-753
19	EE	Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai: An LSI for VDD-hopping and MPEG4 system based on the chip. ISCAS (4) 2001: 918-921
18	EE	Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai: Variable threshold CMOS (VTCMOS) in series connected circuits. ISLPED 2001: 201-206
17	EE	Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai: Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ISLPED 2001: 283-286
16	EE	Youngsoo Shin, Takayasu Sakurai: Estimation of power distribution in VLSI interconnects. ISLPED 2001: 370-375
2000
15	EE	Seongsoo Lee, Takayasu Sakurai: Run-time power control scheme using software feedback loop for low-power real-time application. ASP-DAC 2000: 381-386
14	EE	Koichi Nose, Takayasu Sakurai: Optimization of VDD and VTH for low-power and high speed applications. ASP-DAC 2000: 469-474
13	EE	Nguyen Minh Duc, Takayasu Sakurai: Compact yet high performance (CyHP) library for short time-to-market with new technologies. ASP-DAC 2000: 475-480
12	EE	Takayasu Sakurai: Design challenges for 0.1um and beyond: embedded tutorial. ASP-DAC 2000: 553-558
11	EE	Seongsoo Lee, Takayasu Sakurai: Run-time voltage hopping for low-power real-time systems. DAC 2000: 806-809
10		Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai: Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. ICCAD 2000: 365-368
9	EE	Koichi Nose, Soo-Ik Chae, Takayasu Sakurai: Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED 2000: 228-230
8	EE	Takayasu Sakurai: Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. ISQED 2000: 417-424
7	EE	Koichi Nose, Takayasu Sakurai: Analysis and future trend of short-circuit power. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1023-1030 (2000)
1998
6		Hiroshi Kawaguchi, Takayasu Sakurai: Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. ASP-DAC 1998: 35-43
5	EE	Koichi Nose, Takayasu Sakurai: Integrated Current Sensing Device for Micro IDDQ Test. Asian Test Symposium 1998: 323-326
1996
4	EE	Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai: Substrate noise influence on circuit performance in variable threshold-voltage scheme. ISLPED 1996: 309-312
3	EE	Tadahiro Kuroda, Takayasu Sakurai: Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design. VLSI Signal Processing 13(2-3): 191-201 (1996)
1993
2		Takayasu Sakurai: High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage. ISCAS 1993: 1487-1490
1992
1	EE	Takayasu Sakurai, Bill Lin, A. Richard Newton: Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 228-234 (1992)

Coauthor Index

1	Jin-Hong Ahn	[24]
2	Kazuo Aisaka	[27]
3	Danardono Dwi Antono	[31] [34] [40]
4	Toshiyuki Aritsuka	[27]
5	Kerry Bernstein	[26]
6	David Blaauw (David T. Blaauw)	[26]
7	Soo-Ik Chae	[9]
8	H.-Y. Choi	[35]
9	Hoon-Dae Choi	[28]
10	Hun-Dae Choi	[35]
11	Hyun-Young Choi	[28]
12	Kiyoung Choi	[10]
13	Jin-Yong Chung	[24]
14	Nguyen Minh Duc	[13]
15	Jerry Frenkil	[26]
16	Tetsuya Fujita	[4]
17	Masayuki Hirabayashi	[17]
18	Toshiro Hiramoto	[18]
19	Mark Horowitz	[26]
20	Kenichi Inagaki	[28] [31] [34]
21	Mari Inoue	[37]
22	Takashi Inukai	[18]
23	Koichiro Ishibashi	[27]
24	Koichi Ishida	[36] [38] [43] [45]
25	Hiroki Ishikuro	[38]
26	Masakazu Kakumu	[4]
27	Kouichi Kanda	[28]
28	Hiroshi Kawaguchi	[6] [19] [27] [28] [29] [30] [31] [33] [34] [35] [39] [40]
29	Daejeong Kim	[28]
30	Dong Myong Kim	[28]
31	Young-Hee Kim	[24]
32	Tadahiro Kuroda	[3] [4] [32] [37]
33	Seongsoo Lee	[11] [15] [19] [21]
34	Seungjun Lee	[21]
35	Bill Lin	[1]
36	Kenji Matsuo	[4]
37	Kyeong-Sik Min	[24] [28] [35]
38	Satoshi Misaka	[27]
39	Shinji Mita	[4]
40	Noriyuki Miura	[32] [37]
41	Daisuke Mizoguchi	[32]
42	Masayuki Mizuno	[37]
43	Toshiaki Mori	[4]
44	Masami Murakata	[43] [45]
45	Yoshihiro Nakagawa	[37]
46	Wolfgang Nebel	[26]
47	A. Richard Newton	[1]
48	Kiichi Niitsu	[37]
49	Taro Niiyama	[43] [45]
50	Koichi Nose	[5] [7] [9] [14] [17] [23]
51	Jan M. Rabaey	[26]
52	Fayez Robert Saliba	[28] [39]
53	Youngsoo Shin	[10] [16] [20] [29]
54	Dennis Sylvester	[26]
55	Masamoto Tago	[37]
56	Makoto Takamiya	[38] [43] [45]
57	Atit Tamtrakarn	[36] [38]
58	Keisuke Toyama	[27]
59	Canh Quang Tran	[30] [33]
60	Kunio Uchiyama	[27]
61	Andrew Yang	[26]
62	Gang Zhang	[19]
63	Piao Zhe	[43] [45]

Colors in the list of coauthors