2008 |
27 | EE | Wido Kruijtzer,
Pieter van der Wolf,
Erwin A. de Kock,
Jan Stuyt,
Wolfgang Ecker,
Albrecht Mayer,
Serge Hustin,
Christophe Amerijckx,
Serge de Paoli,
Emmanuel Vaumorin:
Industrial IP Integration Flows based on IP-XACT Standards.
DATE 2008: 32-37 |
2007 |
26 | EE | Wolfgang Ecker,
Volkan Esen,
Lars Schönberg,
Thomas Steininger,
Michael Velten,
Michael Hull:
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.
DATE 2007: 767-772 |
25 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Michael Velten,
Michael Hull:
Interactive presentation: Implementation of a transaction level assertion framework in SystemC.
DATE 2007: 894-899 |
24 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Michael Velten:
Requirements and Concepts for Transaction Level Assertion Refinement.
IESS 2007: 1-14 |
2006 |
23 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Michael Velten:
Case Study on Transaction Level Modeling.
FDL 2006: 209-215 |
22 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Michael Velten,
Jacob Smit:
IP Library For Temporal SystemC Assertions.
FDL 2006: 301-309 |
21 | EE | Wolfgang Ecker,
Volkan Esen,
Michael Hull,
Thomas Steininger,
Michael Velten:
Requirements and Concepts for Transaction Level Assertions.
ICCD 2006 |
20 | EE | Wolfgang Ecker,
Volkan Esen,
Michael Hull:
Execution semantics and formalisms for multi-abstraction TLM assertions.
MEMOCODE 2006: 93-102 |
2005 |
19 | | Wolfgang Ecker,
Lothar Schrader:
Evolution of Paradigm Shifts in the Automated Design Process of Digital Circuits.
GI Jahrestagung (1) 2005: 313 |
2004 |
18 | EE | P. Jensen,
Wolfgang Ecker,
T. Kruse,
Martin Zambaldi:
SystemVerilog: Interface Based Design.
FDL 2004: 505-518 |
17 | EE | Martin Zambaldi,
Wolfgang Ecker:
Extending the RASSP model for Verification.
FDL 2004: 536-544 |
16 | EE | Martin Zambaldi,
Wolfgang Ecker,
T. Kruse,
W. Müller:
The Formal Simulation Semantics of SystemVerilog.
FDL 2004: 568-578 |
15 | EE | Wolfgang Ecker,
Volkan Esen,
Thomas Steininger,
Martin Zambaldi:
Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking.
ISORC 2004: 129-135 |
14 | EE | Martin Zambaldi,
Wolfgang Ecker:
How to Bridge the Gap Between Simulationand Test.
ITC 2004: 1091-1099 |
13 | EE | Martin Zambaldi,
Wolfgang Ecker,
Renate Henftling,
Matthias Bauer:
A Layered Adaptive Verification Platform for Simulation, Test, and Emulation.
IEEE Design & Test of Computers 21(6): 464-471 (2004) |
2003 |
12 | EE | Renate Henftling,
Andreas Zinn,
Matthias Bauer,
Martin Zambaldi,
Wolfgang Ecker:
Re-use-centric architecture for a fully accelerated testbench environment.
DAC 2003: 372-375 |
11 | EE | Renate Henftling,
Andreas Zinn,
Matthias Bauer,
Wolfgang Ecker,
Martin Zambaldi:
Platform-Based Testbench Generation.
DATE 2003: 11038-11045 |
10 | EE | Renate Henftling,
Wolfgang Ecker,
Andreas Zinn,
Martin Zambaldi,
Matthias Bauer:
An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures.
IPDPS 2003: 187 |
1999 |
9 | EE | Matthias Bauer,
Wolfgang Ecker,
Renate Henftling,
Andreas Zinn:
A Method for Accelerating Test Environments.
EUROMICRO 1999: 1477-1480 |
1997 |
8 | EE | Matthias Bauer,
Wolfgang Ecker:
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach.
DAC 1997: 774-779 |
7 | EE | Michael Mrva,
Mike Heuchling,
Wolfgang Ecker:
The Shall-Prototype-Test Development model.
ECBS 1997: 385-391 |
1995 |
6 | EE | Wolfgang Ecker:
Semi-dynamic scheduling of synchronization-mechanisms.
EURO-DAC 1995: 374-379 |
5 | EE | Wolfgang Ecker,
Manfred Huber:
VHDL-based communication and synchronization synthesis.
EURO-DAC 1995: 458-462 |
4 | EE | Wolfgang Ecker:
A classification of design steps and their verification.
EURO-DAC 1995: 536-541 |
1994 |
3 | EE | Wolfgang Ecker,
Manfred Glesner,
Andreas Vombach:
Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations.
EURO-DAC 1994: 624-629 |
1993 |
2 | | Wolfgang Ecker,
Sabine März:
System-Level Specification and Design Using VHDL: A Case Study.
CHDL 1993: 505-522 |
1 | EE | Wolfgang Ecker,
M. Hofmeister:
State look ahead technique for cycle optimization of interacting finite state Moore machines.
ICCAD 1993: 392-397 |