2007 |
12 | EE | Aseem Agarwal,
Kaviraj Chopra,
David Blaauw:
Statistical Timing Based Optimization using Gate Sizing
CoRR abs/0710.4697: (2007) |
2005 |
11 | EE | Aseem Agarwal,
Kaviraj Chopra,
David Blaauw,
Vladimir Zolotov:
Circuit optimization using statistical static timing analysis.
DAC 2005: 321-324 |
10 | EE | Aseem Agarwal,
Kaviraj Chopra,
David Blaauw:
Statistical Timing Based Optimization using Gate Sizing.
DATE 2005: 400-405 |
2004 |
9 | EE | Aseem Agarwal,
Florentin Dartu,
David Blaauw:
Statistical gate delay model considering multiple input switching.
DAC 2004: 658-663 |
8 | EE | Aseem Agarwal,
Vladimir Zolotov,
David Blaauw:
Statistical clock skew analysis considering intradie-process variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1231-1242 (2004) |
2003 |
7 | EE | Aseem Agarwal,
David Blaauw,
Vladimir Zolotov,
Sarma B. K. Vrudhula:
Computation and Refinement of Statistical Bounds on Circuit Delay.
DAC 2003: 348-353 |
6 | EE | Aseem Agarwal,
David Blaauw,
Vladimir Zolotov,
Sarma B. K. Vrudhula:
Statistical Timing Analysis Using Bounds.
DATE 2003: 10062-10067 |
5 | EE | Aseem Agarwal,
David Blaauw,
Vladimir Zolotov:
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations.
ICCAD 2003: 900-907 |
4 | EE | Aseem Agarwal,
David Blaauw,
Vladimir Zolotov:
Statistical Clock Skew Analysis Considering Intra-Die Process Variations.
ICCAD 2003: 914-921 |
3 | EE | Aseem Agarwal,
Vladimir Zolotov,
David T. Blaauw:
Statistical timing analysis using bounds and selective enumeration.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1243-1260 (2003) |
2002 |
2 | EE | Aseem Agarwal,
David Blaauw,
Vladimir Zolotov,
Sarma B. K. Vrudhula:
Statistical timing analysis using bounds and selective enumeration.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 16-21 |
1 | EE | Aseem Agarwal,
David Blaauw,
Vladimir Zolotov,
Sarma B. K. Vrudhula:
Statistical timing analysis using bounds and selective enumeration.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 29-36 |