2007 |
23 | EE | Roberto Bruttomesso,
Alessandro Cimatti,
Anders Franzén,
Alberto Griggio,
Ziyad Hanna,
Alexander Nadel,
Amit Palti,
Roberto Sebastiani:
A Lazy and Layered SMT($\mathcal{BV}$) Solver for Hard Industrial Verification Problems.
CAV 2007: 547-560 |
22 | EE | Ziyad Hanna:
Abstract Modeling and Formal Verification of Microprocessors.
CSR 2007: 23 |
21 | EE | Daher Kaiss,
Marcelo Skaba,
Ziyad Hanna,
Zurab Khasidashvili:
Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.
FMCAD 2007: 20-26 |
20 | EE | Nachum Dershowitz,
Ziyad Hanna,
Alexander Nadel:
Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver.
SAT 2007: 287-293 |
19 | EE | Jacob Katz,
Ziyad Hanna,
Nachum Dershowitz:
Space-Efficient Bounded Model Checking
CoRR abs/0710.4629: (2007) |
2006 |
18 | EE | Sung-Jui (Song-Ra) Pan,
Kwang-Ting Cheng,
John Moondanos,
Ziyad Hanna:
Generation of shorter sequences for high resolution error diagnosis using sequential SAT.
ASP-DAC 2006: 25-29 |
17 | EE | Zurab Khasidashvili,
Marcelo Skaba,
Daher Kaiss,
Ziyad Hanna:
Post-reboot Equivalence and Compositional Verification of Hardware.
FMCAD 2006: 11-18 |
16 | EE | Nachum Dershowitz,
Ziyad Hanna,
Alexander Nadel:
A Scalable Algorithm for Minimal Unsatisfiable Core Extraction.
SAT 2006: 36-41 |
15 | EE | Nachum Dershowitz,
Ziyad Hanna,
Alexander Nadel:
A Scalable Algorithm for Minimal Unsatisfiable Core Extraction
CoRR abs/cs/0605085: (2006) |
14 | EE | Marco Bozzano,
Roberto Bruttomesso,
Alessandro Cimatti,
Anders Franzén,
Ziyad Hanna,
Zurab Khasidashvili,
Amit Palti,
Roberto Sebastiani:
Encoding RTL Constructs for MathSAT: a Preliminary Report.
Electr. Notes Theor. Comput. Sci. 144(2): 3-14 (2006) |
2005 |
13 | EE | Jacob Katz,
Ziyad Hanna,
Nachum Dershowitz:
Space-Efficient Bounded Model Checking.
DATE 2005: 686-687 |
12 | EE | Zurab Khasidashvili,
Alexander Nadel,
Amit Palti,
Ziyad Hanna:
Simultaneous SAT-Based Model Checking of Safety Properties.
Haifa Verification Conference 2005: 56-75 |
11 | EE | Nachum Dershowitz,
Ziyad Hanna,
Jacob Katz:
Bounded Model Checking with QBF.
SAT 2005: 408-414 |
10 | EE | Nachum Dershowitz,
Ziyad Hanna,
Alexander Nadel:
A Clause-Based Heuristic for SAT Solvers.
SAT 2005: 46-60 |
9 | EE | Yulik Feldman,
Nachum Dershowitz,
Ziyad Hanna:
Parallel Multithreaded Satisfiability Solver: Design and Implementation.
Electr. Notes Theor. Comput. Sci. 128(3): 75-90 (2005) |
2004 |
8 | EE | Zurab Khasidashvili,
Marcelo Skaba,
Daher Kaiss,
Ziyad Hanna:
Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints.
ICCAD 2004: 58-65 |
7 | EE | Feng Lu,
Li-C. Wang,
Kwang-Ting (Tim) Cheng,
John Moondanos,
Ziyad Hanna:
A Signal Correlation Guided Circuit-SAT Solver.
J. UCS 10(12): 1629-1654 (2004) |
2003 |
6 | EE | Feng Lu,
Li-C. Wang,
Kwang-Ting Cheng,
John Moondanos,
Ziyad Hanna:
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
DAC 2003: 436-441 |
5 | EE | Zurab Khasidashvili,
Ziyad Hanna:
SAT-based methods for sequential hardware equivalence verification without synchronization.
Electr. Notes Theor. Comput. Sci. 89(4): (2003) |
4 | EE | Gunnar Andersson,
Per Bjesse,
Byron Cook,
Ziyad Hanna:
Design automation with mixtures of proof strategies for propositional logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1042-1048 (2003) |
2002 |
3 | EE | Gunnar Andersson,
Per Bjesse,
Byron Cook,
Ziyad Hanna:
A proof engine approach to solving combinational design automation problems.
DAC 2002: 725-730 |
2 | EE | Sasha Novakovsky,
Shy Shyman,
Ziyad Hanna:
High capacity and automatic functional extraction tool for industrial VLSI circuit designs.
ICCAD 2002: 520-525 |
2001 |
1 | EE | John Moondanos,
Carl-Johan H. Seger,
Ziyad Hanna,
Daher Kaiss:
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.
CAV 2001: 131-143 |