Mahesh Mehendale

2006
31	EE	Mahesh Mehendale: SoC - The Road Ahead. VLSI Design 2006: 40
30	EE	Subash G. Chandar, Mahesh Mehendale, R. Govindarajan: Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. VLSI Signal Processing 44(3): 245-267 (2006)
2004
29	EE	Mahesh Mehendale: Challenges in the Design of Embedded Real-time DSP SoCs. VLSI Design 2004: 507-511
2003
28	EE	Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei: Emerging markets: design goes global. DAC 2003: 195
27	EE	Amitabh Menon, S. K. Nandy, Mahesh Mehendale: Multivoltage scheduling with voltage-partitioned variable storage. ISLPED 2003: 298-301
2001
26	EE	Subash G. Chandar, Mahesh Mehendale, R. Govindarajan: Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. ICCAD 2001: 631-634
25		Mahesh Mehendale, Santhosh Kumar Amanna: Functional Verification of Programmable DSP Cores. VLSI Design 2001: 16-17
24	EE	Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair: Performance Considerations in Embedded DSP based System-On-a-Chip Designs. VLSI Design 2001: 36-41
23	EE	Vikas Agrawal, Anand Pande, Mahesh Mehendale: High Level Synthesis Of Multi-Precision Data Flow Graphs. VLSI Design 2001: 411-416
2000
22		Mahesh Mehendale, Sunil D. Sherlekar: Power Reduction Techniques for Portable DSP Applications. VLSI Design 2000: 3
21	EE	M. N. Mahesh, Mahesh Mehendale: Low Power Realization of Residue Number System Based FIR Filters. VLSI Design 2000: 30-33
1999
20	EE	M. N. Mahesh, Mahesh Mehendale: Improving performance of high precision signal processing algorithms on programmable DSPs. ISCAS (3) 1999: 488-491
19	EE	M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale: Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. VLSI Design 1999: 340-345
18		Mahesh Mehendale, Sunil D. Sherlekar: Low Power Code Generation of Multiplication-free Linear Transforms. VLSI Design 1999: 42-47
1998
17		Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar: Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. ASP-DAC 1998: 151-156
16	EE	Amit Sinha, Mahesh Mehendale: mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. VLSI Design 1998: 104-109
15	EE	Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh: Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. VLSI Design 1998: 110-115
14	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. VLSI Design 1998: 12-17
13	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Extensions to Programmable DSP architectures for Reduced Power Dissipation. VLSI Design 1998: 37-
12	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Low-power realization of FIR filters on programmable DSPs. IEEE Trans. VLSI Syst. 6(4): 546-553 (1998)
1997
11	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. VLSI Design 1997: 124-129
1996
10	EE	Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar: Optimized Code Generation of Multiplication-free Linear Transforms. DAC 1996: 41-46
9	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Low power realization of FIR filters using multirate architectures. VLSI Design 1996: 370-375
1995
8	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Techniques for low power realization for FIR filters. ASP-DAC 1995
7	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Synthesis of multiplier-less FIR filters with minimum number of additions. ICCAD 1995: 668-671
6	EE	Mahesh Mehendale, M. K. Ram Prasad: AATMA: an algorithm for technology mapping for antifuse-based FPGAs. VLSI Design 1995: 69-74
1994
5		Mahesh Mehendale: Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. VLSI Design 1994: 233-236
4		Mahesh Mehendale, Biswadip Mitra: An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. VLSI Design 1994: 369-372
1993
3	EE	Mahesh Mehendale: MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. DAC 1993: 219-223
2		Mahesh Mehendale, Kaushik Roy: Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. VLSI Design 1993: 100-103
1991
1		Mahesh Mehendale, P. Murugavel, M. Poornima: SLIM: A System for ASIC Library Management. ICCAD 1991: 144-147

Coauthor Index

1	Vikas Agrawal	[23]
2	Santhosh Kumar Amanna	[25]
3	Chi-Foon Chan	[28]
4	Subash G. Chandar	[26] [30]
5	R. Govindarajan	[26] [30]
6	Satrajit Gupta	[19]
7	Ajit Gupte	[24]
8	Deirdre Hanford	[28]
9	M. N. Mahesh	[19] [20] [21]
10	Amitabh Menon	[27]
11	Biswadip Mitra	[4]
12	P. Murugavel	[1]
13	Deepa Nair	[24]
14	S. K. Nandy (Soumitra Kumar Nandy)	[27]
15	Jian Yue Pan	[28]
16	Anand Pande	[23]
17	M. Poornima	[1]
18	M. K. Ram Prasad	[6]
19	Ramesh Ramamritham	[24]
20	Kaushik Roy	[2]
21	Somdipta Basu Roy	[15]
22	Narendra V. Shenoy	[28]
23	Sunil D. Sherlekar	[7] [8] [9] [10] [11] [12] [13] [14] [15] [17] [18] [22]
24	Amit Sinha	[16] [17]
25	A. Vasudevan	[28]
26	G. Venkatesh	[7] [8] [9] [10] [11] [12] [13] [14] [15]
27	Shaojun Wei	[28]

Colors in the list of coauthors