2007 |
6 | EE | Vikram Iyengar,
Jinjun Xiong,
Subbayyan Venkatesan,
Vladimir Zolotov,
David E. Lackey,
Peter A. Habitz,
Chandu Visweswariah:
Variation-aware performance verification using at-speed structural test and statistical timing.
ICCAD 2007: 405-412 |
5 | EE | Vikram Iyengar,
Kenneth Pichamuthu,
Andrew Ferko,
Frank Woytowich,
David E. Lackey,
Gary Grise,
Mark Taylor,
Mike Degregorio,
Steven F. Oakland:
An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs.
VTS 2007: 173-178 |
2003 |
4 | EE | David E. Lackey,
Paul S. Zuchowski,
Jürgen Koehl:
Designing mega-ASICs in nanogate technologies.
DAC 2003: 770-775 |
2002 |
3 | EE | David E. Lackey,
Paul S. Zuchowski,
Thomas R. Bednar,
Douglas W. Stout,
Scott W. Gould,
John M. Cohn:
Managing power and performance for System-on-Chip designs using Voltage Islands.
ICCAD 2002: 195-202 |
2 | EE | George W. Doerre,
David E. Lackey:
The IBM ASIC/SoC methodology - A recipe for first-time success.
IBM Journal of Research and Development 46(6): 649-660 (2002) |
1996 |
1 | | James J. Engel,
Thomas S. Guzowski,
Anderson Hunt,
David E. Lackey,
Lansing D. Pickup,
Robert A. Proctor,
Karla Reynolds,
Ann Marie Rincon,
David R. Stauffer:
Design methodology for IBM ASIC products.
IBM Journal of Research and Development 40(4): 387-406 (1996) |