Masud H. Chowdhury

2008
22	EE	Jingye Xu, Pervez Khaled, Masud H. Chowdhury: Fast bus waveform estimation at the presence of coupling noise. ACM Great Lakes Symposium on VLSI 2008: 339-342
21	EE	Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled: Innovative power gating for leakage reduction. ISCAS 2008: 1568-1571
20	EE	Abinash Roy, Masud H. Chowdhury: Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. ISCAS 2008: 2426-2429
19	EE	M. Sajjad Rahaman, Masud H. Chowdhury: Time diversity approach for intra-chip RF/wireless interconnect systems. ISCAS 2008: 2434-2437
18	EE	Jingye Xu, Abinash Roy, Masud H. Chowdhury: Optimization technique for flip-flop inserted global interconnect. ISCAS 2008: 3386-3389
17	EE	Jingye Xu, Pervez Khaled, Masud H. Chowdhury: Full waveform accuracy to estimate delay in coupled digital circuits. ISCAS 2008: 3414-3417
16	EE	Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled: Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip. ISVLSI 2008: 437-440
2007
15	EE	Abinash Roy, Noha Mahmoud, Masud H. Chowdhury: Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. DAC 2007: 184-187
14	EE	Jingye Xu, Abinash Roy, Masud H. Chowdhury: Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. DATE 2007: 1218-1223
13	EE	Jingye Xu, Abinash Roy, Masud H. Chowdhury: Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. ISCAS 2007: 3716-3719
12	EE	Abinash Roy, Noha Mahmoud, Masud H. Chowdhury: Delay and Clock Skew Variation due to Coupling Capacitance and Inductance. ISCAS 2007: 621-624
11	EE	Abinash Roy, Masud H. Chowdhury: Global Interconnect Optimization in the Presence of On-chip Inductance. ISCAS 2007: 885-888
2006
10	EE	V. P. Nigam, Masud H. Chowdhury, Roland Priemer: Separation of Individual Noise Sources from Compound Noise Measurements in Digital Circuits. APCCAS 2006: 1603-1606
9	EE	Vivek Nigam, Masud H. Chowdhury, Roland Priemer: Compound noise analysis in digital circuits using blind source separation. ISCAS 2006
8	EE	Masud H. Chowdhury, Yehea I. Ismail: Realistic scalability of noise in dynamic circuits. IEEE Trans. VLSI Syst. 14(6): 637-641 (2006)
2005
7	EE	Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail: Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. DSN 2005: 770-779
6	EE	Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail: Realizable reduction of interconnect circuits including self and mutual inductances. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 271-277 (2005)
2004
5	EE	Masud H. Chowdhury, Yehea I. Ismail: Possible Noise Failure Modes in Static and Dynamic Circuits. IWSOC 2004: 123-126
2003
4	EE	Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail: Realizable RLCK circuit crunching. DAC 2003: 226-231
3	EE	Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter: Realizable reduction of RLC circuits using node elimination. ISCAS (3) 2003: 494-497
2	EE	Masud H. Chowdhury, Yehea I. Ismail: Analysis of Coupling Noise in Dynamic Circuit. IWSOC 2003: 320-325
2002
1	EE	Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter: Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ISCAS (4) 2002: 197-200

Coauthor Index

1	Chirayu S. Amin	[3] [4] [6]
2	Juliana Gjanci	[16] [21]
3	Yehea I. Ismail	[1] [2] [3] [4] [5] [6] [7] [8]
4	Chandramouli V. Kashyap	[1] [3]
5	Pervez Khaled	[16] [17] [21] [22]
6	Byron Krauter	[1] [3]
7	Noha Mahmoud	[12] [15]
8	Arindam Mallik	[7]
9	Gokhan Memik	[7]
10	V. P. Nigam	[10]
11	Vivek Nigam	[9]
12	Roland Priemer	[9] [10]
13	M. Sajjad Rahaman	[19]
14	Abinash Roy	[11] [12] [13] [14] [15] [18] [20]
15	Jingye Xu	[13] [14] [17] [18] [22]

Colors in the list of coauthors