2008 | ||
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165 | Aarti Gupta, Sharad Malik: Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings Springer 2008 | |
164 | EE | Kaiyu Chen, Sharad Malik, Priyadarsan Patra: Runtime validation of memory ordering using constraint graph checking. HPCA 2008: 415-426 |
163 | EE | Kaiyu Chen, Sharad Malik, Priyadarsan Patra: Runtime Validation of Transactional Memory Systems. ISQED 2008: 750-756 |
162 | EE | Sharad Malik: Hardware Verification: Techniques, Methodology and Solutions. TACAS 2008: 1 |
161 | EE | Yinlei Yu, Cameron Brien, Sharad Malik: Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers. VLSI Design 2008: 461-468 |
160 | EE | Sanjai Narain, Gary Levin, Sharad Malik, Vikram Kaul: Declarative Infrastructure Configuration Synthesis and Debugging. J. Network Syst. Manage. 16(3): 235-258 (2008) |
2007 | ||
159 | EE | Yogesh S. Mahajan, Sharad Malik: Automating Hazard Checking in Transaction-Level Microarchitecture Models. FMCAD 2007: 62-65 |
158 | EE | Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin: Verification Driven Formal Architecture and Microarchitecture Modeling. MEMOCODE 2007: 123-132 |
157 | EE | Zhaohui Fu, Sharad Malik: Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions. VLSI Design 2007: 37-42 |
156 | EE | Xinping Zhu, Sharad Malik: A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. ACM Trans. Design Autom. Electr. Syst. 12(1): (2007) |
2006 | ||
155 | EE | Cameron Brien, Sharad Malik: Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis. FMCAD 2006: 49-50 |
154 | EE | Zhaohui Fu, Sharad Malik: Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. ICCAD 2006: 852-859 |
153 | EE | Kaiyu Chen, Sharad Malik: Dependable Multithreaded Processing Using Runtime Validation. PRDC 2006: 275-286 |
152 | EE | Yinlei Yu, Sharad Malik: Lemma Learning in SMT on Linear Constraints. SAT 2006: 142-155 |
151 | EE | Zhaohui Fu, Sharad Malik: On Solving the Partial MAX-SAT Problem. SAT 2006: 252-265 |
150 | EE | Daijue Tang, Sharad Malik: Solving Quantified Boolean Formulas with Circuit Observability Don't Cares. SAT 2006: 368-381 |
149 | EE | Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, Sharad Malik, David I. August: The Liberty Simulation Environment: A deliberate approach to high-level system modeling. ACM Trans. Comput. Syst. 24(3): 211-249 (2006) |
148 | EE | Xinping Zhu, Wei Qin, Sharad Malik: Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. IEEE Trans. VLSI Syst. 14(7): 707-716 (2006) |
2005 | ||
147 | EE | Yinlei Yu, Sharad Malik: Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice. ASP-DAC 2005: 1047-1051 |
146 | EE | Daijue Tang, Sharad Malik, Aarti Gupta, C. Norris Ip: Symmetry Reduction in SAT-Based Model Checking. CAV 2005: 125-138 |
145 | EE | Fen Xie, Margaret Martonosi, Sharad Malik: Efficient behavior-driven runtime dynamic voltage scaling policies. CODES+ISSS 2005: 105-110 |
144 | EE | Zhaohui Fu, Yinlei Yu, Sharad Malik: Considering Circuit Observability Don't Cares in CNF Satisfiability. DATE 2005: 1108-1113 |
143 | EE | Hangsheng Wang, Li-Shiuan Peh, Sharad Malik: A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks. DATE 2005: 1238-1243 |
142 | EE | Sharad Malik: A Case for Runtime Validation of Hardware. Haifa Verification Conference 2005: 30-42 |
141 | Ali Alphan Bayazit, Sharad Malik: Complementary use of runtime validation and model checking. ICCAD 2005: 1052-1059 | |
140 | EE | Fen Xie, Margaret Martonosi, Sharad Malik: Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation. ISLPED 2005: 287-292 |
139 | EE | Wei Qin, Sharad Malik: A Study of Architecture Description Languages from a Model-based Perspective. MTV 2005: 3-11 |
138 | EE | David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai, Manish Vachharajani, Paul Willmann: Achieving Structural and Composable Modeling of Complex Systems. International Journal of Parallel Programming 33(2-3): 81-101 (2005) |
2004 | ||
137 | Sharad Malik, Limor Fix, Andrew B. Kahng: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004 ACM 2004 | |
136 | EE | Xinping Zhu, Wei Qin, Sharad Malik: Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. CODES+ISSS 2004: 66-71 |
135 | EE | Manish Vachharajani, Neil Vachharajani, Sharad Malik, David I. August: Facilitating reuse in hardware models with enhanced type inference. CODES+ISSS 2004: 86-91 |
134 | EE | Xinping Zhu, Sharad Malik: Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing. DATE 2004: 1244-1249 |
133 | EE | David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai: Achieving Structural and Composable Modeling of Complex Systems. IPDPS Next Generation Software Program - NSFNGS - PI Workshop 2004 |
132 | EE | Wei Qin, Subramanian Rajagopalan, Sharad Malik: A formal concurrency model based architecture description language for synthesis of software development tools. LCTES 2004: 47-56 |
131 | EE | Darsh P. Ranjan, Daijue Tang, Sharad Malik: A Comparative Study of 2QBF Algorithms. SAT 2004 |
130 | EE | Daijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik: Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. SAT 2004 |
129 | EE | Daijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik: Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. SAT (Selected Papers 2004: 292-305 |
128 | EE | Yogesh S. Mahajan, Zhaohui Fu, Sharad Malik: Zchaff2004: An Efficient SAT Solver. SAT (Selected Papers 2004: 360-375 |
127 | EE | Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo: The design of dynamically reconfigurable datapath coprocessors. ACM Trans. Embedded Comput. Syst. 3(2): 361-384 (2004) |
126 | EE | Carl Pixley, Sharad Malik: Guest Editors' Introduction: Exploring Synergies for Design Verification. IEEE Design & Test of Computers 21(6): 461-463 (2004) |
125 | EE | Fen Xie, Margaret Martonosi, Sharad Malik: Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. TACO 1(3): 323-367 (2004) |
2003 | ||
124 | EE | Shaojie Wang, Sharad Malik: Synthesizing operating system based device drivers in embedded systems. CODES+ISSS 2003: 37-44 |
123 | EE | Wei Qin, Sharad Malik: Automated synthesis of efficient binary decoders for retargetable software toolkits. DAC 2003: 764-769 |
122 | EE | Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi: Modeling and Integration of Peripheral Devices in Embedded Systems. DATE 2003: 10136-10141 |
121 | EE | Wei Qin, Sharad Malik: Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. DATE 2003: 10556-10561 |
120 | EE | Lintao Zhang, Sharad Malik: Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications. DATE 2003: 10880-10885 |
119 | EE | Hangsheng Wang, Li-Shiuan Peh, Sharad Malik: Power-driven Design of Router Microarchitectures in On-chip Networks. MICRO 2003: 105-116 |
118 | EE | Fen Xie, Margaret Martonosi, Sharad Malik: Compile-time dynamic voltage scaling settings: opportunities and limits. PLDI 2003: 49-62 |
117 | EE | Lintao Zhang, Sharad Malik: Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms. SAT 2003: 287-298 |
116 | EE | Hangsheng Wang, Li-Shiuan Peh, Sharad Malik: A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. IEEE Micro 23(1): 26-35 (2003) |
2002 | ||
115 | EE | Lintao Zhang, Sharad Malik: The Quest for Efficient Boolean Satisfiability Solvers. CADE 2002: 295-313 |
114 | EE | Lintao Zhang, Sharad Malik: The Quest for Efficient Boolean Satisfiability Solvers. CAV 2002: 17-36 |
113 | EE | Lintao Zhang, Sharad Malik: Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation. CP 2002: 200-215 |
112 | EE | Zhining Huang, Sharad Malik: Exploiting operation level parallelism through dynamically reconfigurable datapaths. DAC 2002: 337-342 |
111 | EE | Gary Smith, Daya Nadamuni, Sharad Malik, Rick Chapman, John Fogelin, Kurt Keutzer, Grant Martin, Brian Bailey: Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? DAC 2002: 479 |
110 | EE | Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik: Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC 2002: 747-750 |
109 | EE | Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh: Design Tools for Application Specific Embedded Processors. EMSOFT 2002: 319-333 |
108 | EE | Hangsheng Wang, Li-Shiuan Peh, Sharad Malik: A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. Hot Interconnects 2002: 21-27 |
107 | EE | Lintao Zhang, Sharad Malik: Conflict driven learning in a quantified Boolean Satisfiability solver. ICCAD 2002: 442-449 |
106 | EE | Xinping Zhu, Sharad Malik: A hierarchical modeling framework for on-chip communication architectures. ICCAD 2002: 663-671 |
105 | EE | Kurt Keutzer, Sharad Malik, A. Richard Newton: From ASIC to ASIP: The Next Design Discontinuity. ICCD 2002: 84-90 |
104 | EE | Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano: Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. ISSS 2002: 38-43 |
103 | EE | Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik: Orion: a power-performance simulator for interconnection networks. MICRO 2002: 294-305 |
102 | Wei Qin, Sharad Malik: Architecture Description Languages for Retargetable Compilation. The Compiler Design Handbook 2002: 535-564 | |
101 | Subramanian Rajagopalan, Sharad Malik: Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors. The Compiler Design Handbook 2002: 603-630 | |
100 | Janett Mohnke, Paul Molitor, Sharad Malik: Limits of Using Signatures for Permutation Independent Boolean Comparison. Formal Methods in System Design 21(2): 167-191 (2002) | |
99 | EE | Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik: Developing Architectural Platforms: A Disciplined Approach. IEEE Design & Test of Computers 19(6): 6-16 (2002) |
2001 | ||
98 | EE | Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik: Optimal Live Range Merge for Address Register Allocation in Embedded Programs. CC 2001: 274-288 |
97 | EE | Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik: Chaff: Engineering an Efficient SAT Solver. DAC 2001: 530-535 |
96 | EE | Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli: Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. DAC 2001: 667-672 |
95 | EE | Zhining Huang, Sharad Malik: Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks. DATE 2001: 735 |
94 | EE | Sharad Malik: Embedded Software Implementation Tools for Fully Programmable Application Specific Systems. EMSOFT 2001: 254-256 |
93 | EE | Lintao Zhang, Conor F. Madigan, Matthew W. Moskewicz, Sharad Malik: Efficient Conflict Driven Learning in Boolean Satisfiability Solver. ICCAD 2001: 279-285 |
92 | EE | Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik: Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. ICCAD 2001: 286-292 |
91 | Ying Zhao, Sharad Malik, Albert Wang, Matthew W. Moskewicz, Conor F. Madigan: Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. ICCD 2001: 447-452 | |
90 | Ying Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan: Accelerating boolean satisfiability through application specific processing. ISSS 2001: 244-249 | |
89 | Kaiyu Chen, Sharad Malik, David I. August: Retargetable static timing analysis for embedded software. ISSS 2001: 39-44 | |
88 | EE | Pranav Ashar, Aarti Gupta, Sharad Malik: Using complete-1-distinguishability for FSM equivalence checking. ACM Trans. Design Autom. Electr. Syst. 6(4): 569-590 (2001) |
87 | EE | Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama: A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1319-1328 (2001) |
86 | EE | Janett Mohnke, Paul Molitor, Sharad Malik: Application of BDDs in Boolean matching techniques for formal logic combinational verification. STTT 3(2): 207-216 (2001) |
2000 | ||
85 | EE | Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik: Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. CASES 2000: 157-164 |
84 | EE | Sharad Malik, D. K. Arvind, Edward A. Lee, Phil Koopman, Alberto L. Sangiovanni-Vincentelli, Wayne Wolf: Embedded systems education (panel abstract). DAC 2000: 519 |
83 | Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh: Incremental CAD. ICCAD 2000: 236-243 | |
82 | EE | Somnath Ghosh, Margaret Martonosi, Sharad Malik: Automated cache optimizations using CME driven diagnosis. ICS 2000: 316-326 |
81 | EE | T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik: Processor Evaluation in an Embedded Systems Design Environment. VLSI Design 2000: 98-103 |
80 | EE | Ashok Sudarsanam, Sharad Malik: Simultaneous reference allocation in code generation for dual data memory bank ASIPs. ACM Trans. Design Autom. Electr. Syst. 5(2): 242-264 (2000) |
79 | EE | Ying Zhao, Sharad Malik: Exact memory size estimation for array computations. IEEE Trans. VLSI Syst. 8(5): 517-521 (2000) |
1999 | ||
78 | EE | Aarti Gupta, Pranav Ashar, Sharad Malik: Exploiting Retiming in a Guided Simulation Based Validation Methodology. CHARME 1999: 350-353 |
77 | EE | Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik: Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. CODES 1999: 2-6 |
76 | EE | Ying Zhao, Sharad Malik: Exact Memory Size Estimation for Array Computations without Loop Unrolling. DAC 1999: 811-816 |
75 | Srinivas Devadas, Sharad Malik, José C. Monteiro, Luciano Lavagno: CAD Techniques for Embedded System Design. VLSI Design 1999: 608 | |
74 | EE | Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe: Performance estimation of embedded software with instruction cache modeling. ACM Trans. Design Autom. Electr. Syst. 4(3): 257-279 (1999) |
73 | EE | Somnath Ghosh, Margaret Martonosi, Sharad Malik: Cache miss equations: a compiler framework for analyzing and tuning memory behavior. ACM Trans. Program. Lang. Syst. 21(4): 703-746 (1999) |
72 | EE | Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik: Using configurable computing to accelerate Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 861-868 (1999) |
71 | EE | Janett Mohnke, Paul Molitor, Sharad Malik: Establishing latch correspondence for sequential circuits using distinguishing signatures. Integration 27(1): 33-46 (1999) |
1998 | ||
70 | EE | Somnath Ghosh, Margaret Martonosi, Sharad Malik: Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity. ASPLOS 1998: 228-239 |
69 | EE | Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi: Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. DAC 1998: 194-199 |
68 | EE | Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik: Accelerating Boolean Satisfiability with Configurable Hardware. FCCM 1998: 186-195 |
67 | EE | Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik: Solving Boolean Satisfiability with Dynamic Hardware Configurations. FPL 1998: 326-335 |
66 | EE | Guido Araujo, Sharad Malik: Code generation for fixed-point DSPs. ACM Trans. Design Autom. Electr. Syst. 3(2): 136-161 (1998) |
65 | EE | Vivek Tiwari, Sharad Malik, Pranav Ashar: Guarded evaluation: pushing power management to logic synthesis/design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1051-1060 (1998) |
1997 | ||
64 | EE | Sharad Malik, Margaret Martonosi, Yau-Tsun Steven Li: Static Timing Analysis of Embedded Software. DAC 1997: 147-152 |
63 | EE | Aarti Gupta, Sharad Malik, Pranav Ashar: Toward Formalizing a Validation Methodology Using Simulation Coverage. DAC 1997: 740-745 |
62 | Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe: Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software. Euro-Par 1997: 1308-1315 | |
61 | EE | Somnath Ghosh, Margaret Martonosi, Sharad Malik: Cache Miss Equations: An Analytical Representation of Cache Misses. International Conference on Supercomputing 1997: 317-324 |
60 | EE | Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez: Dynamic Power Management for Microprocessors: A Case Study. VLSI Design 1997: 185-192 |
59 | EE | Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita: Power analysis and minimization techniques for embedded DSP software. IEEE Trans. VLSI Syst. 5(1): 123-135 (1997) |
58 | EE | Noriya Kobayashi, Sharad Malik: Delay abstraction in combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1205-1212 (1997) |
57 | EE | Yau-Tsun Steven Li, Sharad Malik: Performance analysis of embedded software using implicit path enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1477-1487 (1997) |
1996 | ||
56 | EE | Guido Araujo, Sharad Malik, Mike Tien-Chien Lee: Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. DAC 1996: 591-596 |
55 | EE | Pranav Ashar, Aarti Gupta, Sharad Malik: Using complete-1-distinguishability for FSM equivalence checking. ICCAD 1996: 346-353 |
54 | EE | Vigyan Singhal, Sharad Malik, Robert K. Brayton: The case for retiming with explicit reset circuitry. ICCAD 1996: 618-625 |
53 | EE | Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe: Cache modeling for real-time software: beyond direct mapped instruction caches. IEEE Real-Time Systems Symposium 1996: 254-263 |
52 | EE | Guido Araujo, Ashok Sudarsanam, Sharad Malik: Instruction Set Design and Optimizations for Address Computation in DSP Architectures. ISSS 1996: 102-107 |
51 | EE | Kurt Keutzer, Sharad Malik: Register Transfer Level Synthesis: From Theory to Practice. VLSI Design 1996: 2 |
50 | EE | Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee: Instruction Level Power Analysis and Optimization of Software. VLSI Design 1996: 326-328 |
49 | EE | Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee: Instruction level power analysis and optimization of software. VLSI Signal Processing 13(2-3): 223-238 (1996) |
1995 | ||
48 | EE | Noriya Kobayashi, Sharad Malik: Delay abstraction in combinational logic circuits. ASP-DAC 1995 |
47 | EE | Janett Mohnke, Paul Molitor, Sharad Malik: Limits of using signatures for permutation independent Boolean comparison. ASP-DAC 1995 |
46 | EE | Srinivas Devadas, Sharad Malik: A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. DAC 1995: 242-247 |
45 | EE | Yau-Tsun Steven Li, Sharad Malik: Performance Analysis of Embedded Software Using Implicit Path Enumeration. DAC 1995: 456-461 |
44 | EE | Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe: Performance estimation of embedded software with instruction cache modeling. ICCAD 1995: 380-387 |
43 | EE | Ashok Sudarsanam, Sharad Malik: Memory bank and register allocation in software synthesis for ASIPs. ICCAD 1995: 388-392 |
42 | EE | Pranav Ashar, Sharad Malik: Fast functional simulation using branching programs. ICCAD 1995: 408-412 |
41 | Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe: Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. IEEE Real-Time Systems Symposium 1995: 298-307 | |
40 | EE | Vivek Tiwari, Sharad Malik, Pranav Ashar: Guarded evaluation: pushing power management to logic synthesis/design. ISLPD 1995: 221-226 |
39 | EE | Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita: Power analysis and low-power scheduling techniques for embedded DSP software. ISSS 1995: 110-115 |
38 | EE | Guido Araujo, Sharad Malik: Optimal code generation for embedded memory non-homogeneous register architectures. ISSS 1995: 36-41 |
37 | EE | Anand Raghunathan, Pranav Ashar, Sharad Malik: Test generation for cyclic combinational circuits. VLSI Design 1995: 104-109 |
36 | Yau-Tsun Steven Li, Sharad Malik: Performance Analysis of Embedded Software Using Implicit Path Enumeration. Workshop on Languages, Compilers, & Tools for Real-Time Systems 1995: 88-98 | |
35 | N. Nandhakumar, Sharad Malik: Multisensor Integration for Underwater Scene Classification. Appl. Intell. 5(3): 207-216 (1995) | |
34 | EE | Anand Raghunathan, Pranav Ashar, Sharad Malik: Test generation for cyclic combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1408-1414 (1995) |
33 | EE | Pranav Ashar, Sharad Malik: Functional timing analysis using ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 1025-1030 (1995) |
32 | EE | Pranav Ashar, Sujit Dey, Sharad Malik: Exploiting multicycle false paths in the performance optimization of sequential logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1067-1075 (1995) |
1994 | ||
31 | Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert Wang: Challenges in code generation for embedded processors. Code Generation for Embedded Processors 1994: 48-64 | |
30 | EE | Horng-Fei Jyu, Sharad Malik: Statistical Delay Modeling in Logic Design and Synthesis. DAC 1994: 126-130 |
29 | EE | Pranav Ashar, Sharad Malik: Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. DAC 1994: 77-80 |
28 | EE | Vivek Tiwari, Sharad Malik, Andrew Wolfe: Power analysis of embedded software: a first step towards software power minimization. ICCAD 1994: 384-390 |
27 | EE | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Certified timing verification and the transition delay of a logic circuit. IEEE Trans. VLSI Syst. 2(3): 333-342 (1994) |
26 | EE | Vivek Tiwari, Sharad Malik, Andrew Wolfe: Power analysis of embedded software: a first step towards software power minimization. IEEE Trans. VLSI Syst. 2(4): 437-445 (1994) |
25 | EE | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 814-822 (1994) |
24 | EE | Sharad Malik: Analysis of cyclic combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 950-956 (1994) |
23 | EE | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Verification of asynchronous interface circuits with bounded wire delays. VLSI Signal Processing 7(1-2): 161-182 (1994) |
22 | EE | Teresa H. Y. Meng, Sharad Malik: Editorial. VLSI Signal Processing 7(1-2): 5-6 (1994) |
1993 | ||
21 | EE | Vivek Tiwari, Pranav Ashar, Sharad Malik: Technology Mapping for Lower Power. DAC 1993: 74-79 |
20 | EE | Sharad Malik: Analysis of cyclic combinational circuits. ICCAD 1993: 618-625 |
19 | Horng-Fei Jyu, Sharad Malik: Statistical Timing Optimization of Combinatorial Logic Circuits. ICCD 1993: 77-80 | |
18 | EE | Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer: Statistical timing analysis of combinational logic circuits. IEEE Trans. VLSI Syst. 1(2): 126-137 (1993) |
17 | EE | Srinivas Devadas, Kurt Keutzer, Sharad Malik: Computation of floating mode delay in combinational circuits: theory and algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1913-1923 (1993) |
16 | EE | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1924-1936 (1993) |
15 | EE | Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 568-578 (1993) |
14 | EE | Srinivas Devadas, Kurt Keutzer, Sharad Malik: A synthesis-based test generation and compaction algorithm for multifaults. J. Electronic Testing 4(1): 91-104 (1993) |
1992 | ||
13 | EE | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Certified Timing Verification and the Transition Delay of a Logic Circuit. DAC 1992: 549-555 |
12 | EE | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Verification of asynchronous interface circuits with bounded wire delays. ICCAD 1992: 188-195 |
11 | EE | Pranav Ashar, Sujit Dey, Sharad Malik: Exploiting multi-cycle false paths in the performance optimization of sequential circuits. ICCAD 1992: 510-517 |
10 | Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik: Statistical Timing Analysis of Combinational Circuits. ICCD 1992: 38-43 | |
9 | EE | Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Symbolic minimization of multilevel logic and the input encoding problem. IEEE Trans. on CAD of Integrated Circuits and Systems 11(7): 825-843 (1992) |
1991 | ||
8 | EE | Srinivas Devadas, Kurt Keutzer, Sharad Malik: A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. DAC 1991: 359-365 |
7 | Srinivas Devadas, Kurt Keutzer, Sharad Malik: Delay Computation in Combinational Logic Circuits: Theory and Algorithms. ICCAD 1991: 176-179 | |
6 | EE | Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Retiming and resynthesis: optimizing sequential networks with combinational techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 74-84 (1991) |
5 | EE | Kurt Keutzer, Sharad Malik, Alexander Saldanha: Is redundancy necessary to reduce delay? IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 427-435 (1991) |
1990 | ||
4 | EE | Kurt Keutzer, Sharad Malik, Alexander Saldanha: Is Redundancy Necessary to Reduce Delay. DAC 1990: 228-234 |
3 | Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance Optimization of Pipelined Circuits. ICCAD 1990: 410-413 | |
2 | Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. ICCAD 1990: 560-563 | |
1 | Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton: Algorithms for Discrete Function Manipulation. ICCAD 1990: 92-95 |