Anuja Sehgal

2009
14	EE	Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty: Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers 58(3): 409-423 (2009)
2008
13	EE	Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty: Power-aware SoC test planning for effective utilization of port-scalable testers. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
2007
12	EE	Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty: Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores CoRR abs/0710.4686: (2007)
11	EE	Anuja Sehgal, Krishnendu Chakrabarty: Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. IEEE Trans. Computers 56(1): 120-133 (2007)
2006
10	EE	Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE 2006: 285-290
9	EE	Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty: Test infrastructure design for mixed-signal SOCs with wrapped analog cores. IEEE Trans. VLSI Syst. 14(3): 292-304 (2006)
2005
8	EE	Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty: Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. DATE 2005: 50-55
7		Anuja Sehgal, Krishnendu Chakrabarty: Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. ICCAD 2005: 88-93
6	EE	Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty: A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. ICCD 2005: 137-142
2004
5	EE	Anuja Sehgal, Krishnendu Chakrabarty: Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. DATE 2004: 422-427
4	EE	Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC 2004: 1203-1212
3	EE	Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty: SOC test planning using virtual test access architectures. IEEE Trans. VLSI Syst. 12(12): 1263-1276 (2004)
2003
2	EE	Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty: Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. DAC 2003: 738-743
1	EE	Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty: TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. ICCAD 2003: 95-99

Coauthor Index

1	Sudarshan Bahukudumbi	[13]
2	Krishnendu Chakrabarty	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
3	Sandeep Kumar Goel	[4] [10] [14]
4	Vikram Iyengar	[2] [3]
5	Mark D. Krasniewski	[2]
6	Fang Liu	[8] [12]
7	Erik Jan Marinissen	[4] [10] [14]
8	Sule Ozev	[1] [6] [8] [9] [12]