2005 |
21 | EE | Volkan Kursun,
Gerhard Schrom,
Vivek De,
Eby G. Friedman,
Siva Narendra:
Cascode buffer for monolithic voltage conversion operating at high input supply voltages.
ISCAS (1) 2005: 464-467 |
20 | EE | James Tschanz,
Siva Narendra,
Ali Keshavarzi,
Vivek De:
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.
ISCAS (1) 2005: 9-12 |
19 | EE | Siva Narendra:
Challenges and design choices in nanoscale CMOS.
JETC 1(1): 7-49 (2005) |
2004 |
18 | EE | Arman Vassighi,
Ali Keshavarzi,
Siva Narendra,
Gerhard Schrom,
Yibin Ye,
Seri Lee,
Greg Chrysler,
Manoj Sachdev,
Vivek De:
Design optimizations for microprocessors at low temperature.
DAC 2004: 2-5 |
17 | EE | Gerhard Schrom,
Peter Hazucha,
Jae-Hong Hahn,
Volkan Kursun,
Donald S. Gardner,
Siva Narendra,
Tanay Karnik,
Vivek De:
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.
ISLPED 2004: 263-268 |
16 | EE | Volkan Kursun,
Siva Narendra,
Vivek De,
Eby G. Friedman:
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.
ISQED 2004: 517-521 |
15 | EE | Siva Narendra,
Vasantha Erraguntla,
James Tschanz,
Nitin Borkar:
Design Challenges in Sub-100nm High Performance Microprocessors.
VLSI Design 2004: 15-17 |
14 | EE | K. Narasimhulu,
Siva Narendra,
V. Ramgopal Rao:
The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance.
VLSI Design 2004: 545-550 |
2003 |
13 | EE | Shekhar Borkar,
Tanay Karnik,
Siva Narendra,
James Tschanz,
Ali Keshavarzi,
Vivek De:
Parameter variations and impact on circuits and microarchitecture.
DAC 2003: 338-342 |
12 | EE | Stephen Tang,
Siva Narendra,
Vivek De:
Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation.
ISLPED 2003: 199-204 |
11 | EE | Volkan Kursun,
Siva Narendra,
Vivek De,
Eby G. Friedman:
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization.
ISQED 2003: 279- |
2002 |
10 | EE | James Kao,
Siva Narendra,
Anantha Chandrakasan:
Subthreshold leakage modeling and reduction techniques.
ICCAD 2002: 141-148 |
9 | EE | Siva Narendra,
Vivek De,
Shekhar Borkar,
Dimitri Antoniadis,
Anantha Chandrakasan:
Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS.
ISLPED 2002: 19-23 |
8 | EE | Ron Wilson,
Siva Narendra,
Vivek De:
Evening Panel Discussion: Process Variation: Is It Too Much to Handle?
ISQED 2002: 213- |
7 | EE | Ali Keshavarzi,
James Tschanz,
Siva Narendra,
Vivek De,
W. Robert Daasch,
Kaushik Roy,
Manoj Sachdev,
Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.
IEEE Design & Test of Computers 19(5): 36-43 (2002) |
6 | EE | Fatih Hamzaoglu,
Yibin Ye,
Ali Keshavarzi,
Kevin Zhang,
Siva Narendra,
Shekhar Borkar,
Mircea R. Stan,
Vivek De:
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. VLSI Syst. 10(2): 91-95 (2002) |
2001 |
5 | EE | James Tschanz,
Siva Narendra,
Zhanping Chen,
Shekhar Borkar,
Manoj Sachdev,
Vivek De:
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
ISLPED 2001: 147-152 |
4 | EE | Siva Narendra,
Vivek De,
Dimitri Antoniadis,
Anantha Chandrakasan,
Shekhar Borkar:
Scaling of stack effect and its application for leakage reduction.
ISLPED 2001: 195-200 |
3 | EE | Ali Keshavarzi,
Sean Ma,
Siva Narendra,
B. Bloechel,
K. Mistry,
T. Ghani,
Shekhar Borkar,
Vivek De:
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs.
ISLPED 2001: 207-212 |
1999 |
2 | EE | Ali Keshavarzi,
Siva Narendra,
Shekhar Borkar,
Charles F. Hawkins,
Kaushik Roy,
Vivek De:
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
ISLPED 1999: 252-254 |
1998 |
1 | EE | James Kao,
Siva Narendra,
Anantha Chandrakasan:
MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns.
DAC 1998: 495-500 |