| 2005 |
|---|
| 11 | EE | Heidi E. Ziegler,
Mary W. Hall:
Evaluating heuristics in automatically mapping multi-loop applications to FPGAs.
FPGA 2005: 184-195 |
| 10 | EE | Heidi E. Ziegler,
Priyadarshini L. Malusare,
Pedro C. Diniz:
Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures.
LCPC 2005: 62-75 |
| 9 | EE | Pedro C. Diniz,
Mary W. Hall,
Joonseok Park,
Byoungro So,
Heidi E. Ziegler:
Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system.
Microprocessors and Microsystems 29(2-3): 51-62 (2005) |
| 2004 |
|---|
| 8 | EE | Byoungro So,
Mary W. Hall,
Heidi E. Ziegler:
Custom Data Layout for Memory Parallelism.
CGO 2004: 291-302 |
| 7 | EE | Heidi E. Ziegler:
Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems.
FPL 2004: 1176-1177 |
| 2003 |
|---|
| 6 | EE | Heidi E. Ziegler,
Mary W. Hall,
Pedro C. Diniz:
Compiler-generated communication for pipelined FPGA applications.
DAC 2003: 610-615 |
| 5 | EE | Heidi E. Ziegler,
Mary W. Hall,
Byoungro So:
Search Space Properties for Mapping Coarse-Grain Pipelined FPGA Applications.
LCPC 2003: 1-16 |
| 2002 |
|---|
| 4 | EE | Heidi E. Ziegler,
Byoungro So,
Mary W. Hall,
Pedro C. Diniz:
Coarse-Grain Pipelining on Multiple FPGA Architectures.
FCCM 2002: 77- |
| 2001 |
|---|
| 3 | EE | Pedro C. Diniz,
Mary W. Hall,
Joonseok Park,
Byoungro So,
Heidi E. Ziegler:
Bridging the Gap between Compilation and Synthesis in the DEFACTO System.
LCPC 2001: 52-70 |
| 1999 |
|---|
| 2 | | Kiran Bondalapati,
Pedro C. Diniz,
Phillip Duncan,
John J. Granacki,
Mary W. Hall,
Rajeev Jain,
Heidi E. Ziegler:
DEFACTO: A Design Environment for Adaptive Computing Technology.
IPPS/SPDP Workshops 1999: 570-578 |
| 1998 |
|---|
| 1 | EE | Christopher Ho,
Heidi E. Ziegler,
Michel Dubois:
In-Memory Directories: Eliminating the Cost of Directories in CC-NUMAs.
SPAA 1998: 222-230 |
