2008 |
45 | EE | Carl Pixley:
Practical Considerations Concerning HL-to -RT Equivalence Checking.
Haifa Verification Conference 2008: 6 |
2007 |
44 | EE | Alfred Kölbl,
Jerry R. Burch,
Carl Pixley:
Memory Modeling in ESL-RTL Equivalence Checking.
DAC 2007: 205-209 |
43 | EE | In-Ho Moon,
Per Bjesse,
Carl Pixley:
A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states.
DATE 2007: 1170-1175 |
2006 |
42 | EE | Sandeep K. Shukla,
Carl Pixley,
Gary Smith:
Guest Editors' Introduction: The True State of the Art of ESL Design.
IEEE Design & Test of Computers 23(5): 335-337 (2006) |
2005 |
41 | EE | Alfred Kölbl,
Carl Pixley:
Constructing Efficient Formal Models from High-Level Descriptions Using Symbolic Simulation.
International Journal of Parallel Programming 33(6): 645-666 (2005) |
2004 |
40 | EE | In-Ho Moon,
Carl Pixley:
Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders.
FMCAD 2004: 144-158 |
39 | EE | Carl Pixley,
D. Meyers,
S. McMaster,
A. Chittor:
Designers want proofs - but show me the money.
MEMOCODE 2004: 153-154 |
38 | EE | Carl Pixley,
Sharad Malik:
Guest Editors' Introduction: Exploring Synergies for Design Verification.
IEEE Design & Test of Computers 21(6): 461-463 (2004) |
37 | EE | Jun Yuan,
Adnan Aziz,
Carl Pixley,
Ken Albin:
Simplifying Boolean constraint solving for random simulation-vector generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 412-420 (2004) |
2003 |
36 | EE | Jun Yuan,
Ken Albin,
Adnan Aziz,
Carl Pixley:
Constraint synthesis for environment modeling in functional verification.
DAC 2003: 296-299 |
35 | EE | Rajesh K. Gupta,
Shishpal Rawat,
Sandeep K. Shukla,
Brian Bailey,
Daniel K. Beece,
Masahiro Fujita,
Carl Pixley,
John O'Leary,
Fabio Somenzi:
Formal verification - prove it or pitch it.
DAC 2003: 710-711 |
34 | EE | Jun Yuan,
Carl Pixley,
Adnan Aziz,
Ken Albin:
A Framework for Constrained Functional Verification.
ICCAD 2003: 142-145 |
33 | EE | Vigyan Singhal,
Carl Pixley,
Adnan Aziz,
Shaz Qadeer,
Robert K. Brayton:
Sequential optimization in the absence of global reset.
ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003) |
32 | | Carl Pixley,
Juan Antonio Carballo:
Panel Summaries.
IEEE Design & Test of Computers 20(4): 86-88 (2003) |
2002 |
31 | EE | In-Ho Moon,
Hee-Hwan Kwak,
James H. Kukula,
Thomas R. Shiple,
Carl Pixley:
Simplifying Circuits for Formal Verification Using Parametric Representation.
FMCAD 2002: 52-69 |
30 | EE | Jun Yuan,
Ken Albin,
Adnan Aziz,
Carl Pixley:
Simplifying Boolean constraint solving for random simulation-vector generation.
ICCAD 2002: 123-127 |
29 | | Jun Yuan,
Ken Albin,
Adnan Aziz,
Carl Pixley:
Simplifying Constraint Solving in Random Simulation Generation.
IWLS 2002: 185-190 |
2001 |
28 | EE | Noel R. Strader,
Gérard Memmi,
Carl Pixley:
Application of Formal Verification to Design Creation and Implementation.
ISQED 2001: 11 |
27 | | Carl Pixley:
Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits.
IEEE Design & Test of Computers 18(4): 4-5 (2001) |
26 | EE | Vigyan Singhal,
Carl Pixley,
Adnan Aziz,
Robert K. Brayton:
Theory of safe replacements for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 249-265 (2001) |
2000 |
25 | EE | Jun Yuan,
Kurt Shultz,
Carl Pixley,
Hillel Miller,
Adnan Aziz:
Automatic Vector Generation Using Constraints and Biasing.
J. Electronic Testing 16(1-2): 107-120 (2000) |
24 | EE | Jaehong Park,
Carl Pixley,
Michael Burns,
Hyunwoo Cho:
An Efficient Logic Equivalence Checker for Industrial Circuits.
J. Electronic Testing 16(1-2): 91-106 (2000) |
1999 |
23 | EE | Jun Yuan,
Kurt Shultz,
Carl Pixley,
Hillel Miller,
Adnan Aziz:
Modeling design constraints and biasing in simulation using BDDs.
ICCAD 1999: 584-590 |
22 | | Carl Pixley,
Kurt Shultz,
Jun Yuan:
Integrated Formal and Informal Design Verification of Commercial Integrated Circuits.
PDPTA 1999: 1061-1068 |
21 | EE | Carl Pixley,
Vigyan Singhal:
Model Checking: A Hardware Design Perspective.
STTT 2(3): 288-306 (1999) |
1998 |
20 | EE | Jainendra Kumar,
Carl Pixley:
Logic and Functional Verification in a Commercial Semiconductor Environment.
ACSD 1998: 8-15 |
19 | | Matt Kaufmann,
Andrew Martin,
Carl Pixley:
Design Constraints in Symbolic Model Checking.
CAV 1998: 477-487 |
18 | EE | In-Ho Moon,
Jae-Young Jang,
Gary D. Hachtel,
Fabio Somenzi,
Jun Yuan,
Carl Pixley:
Approximate reachability don't cares for CTL model checking.
ICCAD 1998: 351-358 |
1997 |
17 | EE | Jae-Young Jang,
Shaz Qadeer,
Matt Kaufmann,
Carl Pixley:
Formal Verification of FIRE: A Case Study.
DAC 1997: 173-177 |
16 | | Matt Kaufmann,
Carl Pixley:
Intertwined Development and Formal Verification of a 60x Bus Model.
ICCD 1997: 25-30 |
1996 |
15 | | Carl Pixley,
Noel R. Strader,
W. C. Bruce,
Jaehong Park,
Matt Kaufmann,
Kurt Shultz,
Michael Burns,
Jainendra Kumar,
Jun Yuan,
Janet Nguyen:
Commercial Design Verification: Methodology and Tools.
ITC 1996: 839-848 |
1995 |
14 | EE | Vigyan Singhal,
Carl Pixley,
Richard L. Rudell,
Robert K. Brayton:
The Validity of Retiming Sequential Circuits.
DAC 1995: 316-321 |
13 | EE | Vigyan Singhal,
Carl Pixley,
Adnan Aziz,
Robert K. Brayton:
Exploiting power-up delay for sequential optimization.
EURO-DAC 1995: 54-59 |
12 | | Vigyan Singhal,
Robert K. Brayton,
Carl Pixley:
Power-Up Delay for Retiming Digital Circuits.
ISCAS 1995: 566-569 |
1994 |
11 | | Vigyan Singhal,
Carl Pixley:
The Verifiacation Problem for Safe Replaceability.
CAV 1994: 311-323 |
10 | EE | Carl Pixley,
Vigyan Singhal,
Adnan Aziz,
Robert K. Brayton:
Multi-level synthesis for safe replaceability.
ICCAD 1994: 442-449 |
9 | EE | Carl Pixley,
Seh-Woong Jeong,
Gary D. Hachtel:
Exact calculation of synchronizing sequences based on binary decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1024-1034 (1994) |
1993 |
8 | EE | June-Kyung Rho,
Fabio Somenzi,
Carl Pixley:
Minimum Length Synchronizing Sequences of Finite State Machine.
DAC 1993: 463-468 |
7 | EE | Hyunwoo Cho,
Seh-Woong Jeong,
Fabio Somenzi,
Carl Pixley:
Synchronizing sequences and symbolic traversal techniques in test generation.
J. Electronic Testing 4(1): 19-31 (1993) |
1992 |
6 | EE | Carl Pixley,
Seh-Woong Jeong,
Gary D. Hachtel:
Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams.
DAC 1992: 620-623 |
5 | EE | Carl Pixley:
A theory and implementation of sequential hardware equivalence.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1469-1478 (1992) |
1991 |
4 | | Carl Pixley,
Gary Beihl:
Calculating Resetability and Reset Sequences.
ICCAD 1991: 376-379 |
3 | | Carl Pixley,
Gary Beihl,
Ernesto Pacas-Skewes:
Automatic Derivation of FSM Specification to Implementation Encoding.
ICCD 1991: 245-249 |
1990 |
2 | | Carl Pixley:
Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence.
CAV 1990: 54-64 |
1988 |
1 | | Carl Pixley:
An Incremental Garbage Collection Algorithm for Multi-Mutator Systems.
Distributed Computing 3(1): 41-50 (1988) |