2008 |
48 | EE | Herman Schmit,
Amit Gupta,
Radu Ciobanu:
Placement challenges for structured ASICs.
ISPD 2008: 84-86 |
2005 |
47 | | Herman Schmit,
Steven J. E. Wilton:
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005
ACM 2005 |
46 | EE | Herman Schmit,
Vikas Chandra:
Layout techniques for FPGA switch blocks.
IEEE Trans. VLSI Syst. 13(1): 96-105 (2005) |
2004 |
45 | | Russell Tessier,
Herman Schmit:
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004
ACM 2004 |
44 | EE | R. Reed Taylor,
Herman Schmit:
Enabling energy efficiency in via-patterned gate array devices.
DAC 2004: 874-878 |
43 | EE | Vikas Chandra,
Anthony Xu,
Herman Schmit,
Lawrence T. Pileggi:
An Interconnect Channel Design Methodology for High Performance Integrated Circuits.
DATE 2004: 1138-1143 |
42 | EE | Vikas Chandra,
Herman Schmit,
Anthony Xu,
Lawrence T. Pileggi:
A power aware system level interconnect design methodology for latency-insensitive systems.
ICCAD 2004: 275-282 |
41 | EE | R. Reed Taylor,
Herman Schmit:
Creating a power-aware structured ASIC.
ISLPED 2004: 74-77 |
40 | EE | Theo Theocharides,
Greg M. Link,
Eric J. Swankoski,
Narayanan Vijaykrishnan,
Mary Jane Irwin,
Herman Schmit:
Evaluating Alternative Implementations for LDPC Decoder Check Node Function.
ISVLSI 2004: 77-82 |
39 | EE | Vikas Chandra,
Anthony Xu,
Herman Schmit:
A low power approach to system level pipelined interconnect design.
SLIP 2004: 45-52 |
2003 |
38 | EE | Lawrence T. Pileggi,
Herman Schmit,
Andrzej J. Strojwas,
Padmini Gopalakrishnan,
V. Kheterpal,
Aneesh Koorapaty,
Chetan Patel,
V. Rovner,
K. Y. Tong:
Exploring regular fabrics to optimize the performance-cost trade-off.
DAC 2003: 782-787 |
37 | EE | Aneesh Koorapaty,
Vikas Chandra,
K. Y. Tong,
Chetan Patel,
Lawrence T. Pileggi,
Herman Schmit:
Heterogeneous Programmable Logic Block Architectures.
DATE 2003: 11118-11119 |
36 | EE | Benjamin A. Levine,
Herman Schmit:
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable.
FCCM 2003: 101-110 |
35 | EE | Hiroto Kagotani,
Herman Schmit:
Asynchronous PipeRench: Architecture and Performance Estimations.
FCCM 2003: 121- |
34 | EE | Herman Schmit:
Extra-dimensional Island-Style FPGAs.
FPL 2003: 406-415 |
33 | EE | Aneesh Koorapaty,
Lawrence T. Pileggi,
Herman Schmit:
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.
FPL 2003: 426-436 |
32 | EE | Matthew Moe,
Herman Schmit:
Floorplanning of pipelined array modules using sequence pairs.
ISPD 2003: 143-150 |
31 | EE | Chetan Patel,
Anthony Cozzie,
Herman Schmit,
Lawrence T. Pileggi:
An architectural exploration of via patterned gate arrays.
ISPD 2003: 184-189 |
30 | EE | Herman Schmit,
Thomas Kroll,
Max Khusid,
Ivan S. Kourtev,
Narayanan Vijaykrishnan,
David L. Landis:
The Sandbox Design Experience Course.
MSE 2003: 39-40 |
29 | EE | Thomas Kroll,
Herman Schmit,
Dave Landis:
CAD Tool Support For A Multi-University Soc Certificate Program: The Digital Sandbox.
MSE 2003: 47-48 |
2002 |
28 | EE | David Whelihan,
Herman Schmit:
Memory optimization in single chip network switch fabrics.
DAC 2002: 530-535 |
27 | EE | Herman Schmit,
Benjamin A. Levine,
Benjamin Ylvisaker:
Queue Machines: Hardware Compilation in Hardware.
FCCM 2002: 152- |
26 | EE | Herman Schmit,
Vikas Chandra:
FPGA switch block layout and evaluation.
FPGA 2002: 11-18 |
25 | EE | Silviu M. S. A. Chiricescu,
Michael A. Schuette,
Robin Glinton,
Herman Schmit:
Morphable Multipliers.
FPL 2002: 647-656 |
24 | EE | Vikas Chandra,
Herman Schmit:
Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach.
ISVLSI 2002: 35-40 |
23 | | Silviu M. S. A. Chiricescu,
Michael A. Schuette,
Herman Schmit,
Robin Glinton:
Synthesis of Morphable Multipliers.
IWLS 2002: 109-113 |
2001 |
22 | EE | Pradeep K. Khosla,
Herman Schmit,
Mary Jane Irwin,
Narayanan Vijaykrishnan,
Tom Cain,
Steven P. Levitan,
Dave Landis:
SoC Design Skills: Collaboration Builds a Stronger SoC Design Team.
MSE 2001: 42-43 |
2000 |
21 | EE | Benjamin A. Levine,
R. Reed Taylor,
Herman Schmit:
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware.
FCCM 2000: 217-226 |
20 | EE | Herman Schmit,
Ray Andraka,
Philip Friedin,
Satnam Singh,
Tim Southgate:
The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers.
FPGA 2000: 101 |
19 | EE | Herman Schmit,
David Whelihan,
Peter Kamarchik,
Frank Gennari:
Scalable interconnect and power distribution for island-style FPGAs (poster abstract).
FPGA 2000: 221 |
18 | EE | Yuan C. Chou,
Pazhani Pillai,
Herman Schmit,
John Paul Shen:
PipeRench implementation of the instruction path coprocessor.
MICRO 2000: 147-158 |
17 | | Seth Copen Goldstein,
Herman Schmit,
Mihai Budiu,
Srihari Cadambi,
Matthew Moe,
R. Reed Taylor:
PipeRench: A Reconfigurable Architecture and Compiler.
IEEE Computer 33(4): 70-77 (2000) |
16 | EE | Herman Schmit,
Srihari Cadambi,
Matthew Moe,
Seth Copen Goldstein:
Pipeline Reconfigurable FPGAs.
VLSI Signal Processing 24(2-3): 129-146 (2000) |
1999 |
15 | EE | Christopher Inacio,
Herman Schmit,
David Nagle,
Andrew Ryan,
Donald E. Thomas,
Yingfai Tong,
Ben Klass:
Vertical Benchmarks for CAD.
DAC 1999: 408-413 |
14 | EE | Ronald Laufer,
R. Reed Taylor,
Herman Schmit:
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing.
FCCM 1999: 200-208 |
13 | EE | Herman Schmit:
Extra-Dimensional Island-Style FPGAs.
FPGA 1999: 247 |
12 | EE | Seth Copen Goldstein,
Herman Schmit,
Matthew Moe,
Mihai Budiu,
Srihari Cadambi,
R. Reed Taylor,
Ronald Laufer:
PipeRench: A Coprocessor for Streaming multimedia Acceleration.
ISCA 1999: 28-39 |
11 | EE | Bharath Ramasubramanian,
Herman Schmit,
L. Richard Carley:
Mixed-swing quadrail for low power dual-rail domino logic.
ISLPED 1999: 82-84 |
1998 |
10 | EE | Matthew Moe,
Herman Schmit,
Seth Copen Goldstein:
Characterization and Parameterization of a Pipeline Reconfigurable FPGA.
FCCM 1998: 294- |
9 | EE | Srihari Cadambi,
Jeffrey Weener,
Seth Copen Goldstein,
Herman Schmit,
Donald E. Thomas:
Managing Pipeline-Reconfigurable FPGAs.
FPGA 1998: 55-64 |
8 | EE | Herman Schmit,
Donald E. Thomas:
Address generation for memories containing multiple arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 377-385 (1998) |
1997 |
7 | EE | Herman Schmit:
Incremental reconfiguration for pipelined applications.
FCCM 1997: 47-55 |
6 | EE | Herman Schmit:
Is Reconfigurable Computing Commercially Viable (panel)?
FPGA 1997: 101 |
5 | EE | Herman Schmit,
Donald E. Thomas:
Synthesis of application-specific memory designs.
IEEE Trans. VLSI Syst. 5(1): 101-111 (1997) |
1995 |
4 | EE | Herman Schmit,
Donald E. Thomas:
Hidden Markov modeling and fuzzy controllers in FPGAs.
FCCM 1995: 214-221 |
3 | EE | Herman Schmit,
Donald E. Thomas:
Address generation for memories containing multiple arrays.
ICCAD 1995: 510-514 |
2 | EE | Herman Schmit,
Donald E. Thomas:
Array mapping in behavioral synthesis.
ISSS 1995: 90-95 |
1993 |
1 | EE | Donald E. Thomas,
Jay K. Adams,
Herman Schmit:
A Model and Methodology for Hardware-Software Codesign.
IEEE Design & Test of Computers 10(3): 6-15 (1993) |