| 2008 |
| 22 | EE | Elif Alpaslan,
Yu Huang,
Xijiang Lin,
Wu-Tung Cheng,
Jennifer Dworak:
Reducing Scan Shift Power at RTL.
VTS 2008: 139-146 |
| 21 | EE | Xijiang Lin,
Yu Huang:
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells.
J. Electronic Testing 24(4): 327-334 (2008) |
| 2007 |
| 20 | EE | Santiago Remersaro,
Xijiang Lin,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
Low Shift and Capture Power Scan Tests.
VLSI Design 2007: 793-798 |
| 19 | EE | Matthias Beck,
Olivier Barondeau,
Martin Kaibel,
Frank Poehl,
Xijiang Lin,
Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality
CoRR abs/0710.4763: (2007) |
| 18 | EE | Santiago Remersaro,
Xijiang Lin,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
Scan-Based Tests with Low Switching Activity.
IEEE Design & Test of Computers 24(3): 268-275 (2007) |
| 2006 |
| 17 | EE | Xijiang Lin,
Janusz Rajski:
The Impacts of Untestable Defects on Transition Fault Testing.
VTS 2006: 2-7 |
| 16 | EE | Zhuo Zhang,
Sudhakar M. Reddy,
Irith Pomeranz,
Xijiang Lin,
Janusz Rajski:
Scan Tests with Multiple Fault Activation Cycles for Delay Faults.
VTS 2006: 343-348 |
| 2005 |
| 15 | EE | Xijiang Lin,
Janusz Rajski:
Propagation delay fault: a new fault model to test delay faults.
ASP-DAC 2005: 178-183 |
| 14 | EE | Matthias Beck,
Olivier Barondeau,
Martin Kaibel,
Frank Poehl,
Xijiang Lin,
Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.
DATE 2005: 56-61 |
| 13 | EE | Matthias Beck,
Olivier Barondeau,
Frank Poehl,
Xijiang Lin,
Ron Press:
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study.
VTS 2005: 223-228 |
| 2003 |
| 12 | EE | Xijiang Lin,
Rob Thompson:
Test generation for designs with multiple clocks.
DAC 2003: 662-667 |
| 11 | EE | Xijiang Lin,
Ron Press,
Janusz Rajski,
Paul Reuter,
Thomas Rinderknecht,
Bruce Swanson,
Nagesh Tamarapalli:
High-Frequency, At-Speed Scan Testing.
IEEE Design & Test of Computers 20(5): 17-25 (2003) |
| 2002 |
| 10 | EE | Chen Wang,
Sudhakar M. Reddy,
Irith Pomeranz,
Xijiang Lin,
Janusz Rajski:
Conflict driven techniques for improving deterministic test pattern generation.
ICCAD 2002: 87-93 |
| 9 | EE | Nandu Tendolkar,
Rajesh Raina,
Rick Woltenberg,
Xijiang Lin,
Bruce Swanson,
Greg Aldrich:
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.
VTS 2002: 3-8 |
| 2001 |
| 8 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Xijiang Lin:
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan.
Asian Test Symposium 2001: 467 |
| 7 | | Xijiang Lin,
Janusz Rajski,
Irith Pomeranz,
Sudhakar M. Reddy:
On static test compaction and test pattern ordering for scan designs.
ITC 2001: 1088-1097 |
| 2000 |
| 6 | EE | Xijiang Lin,
Wu-Tung Cheng,
Irith Pomeranz,
Sudhakar M. Reddy:
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.
VTS 2000: 205-212 |
| 1999 |
| 5 | EE | Xijiang Lin,
Irith Pomeranz,
Sudhakar M. Reddy:
Full Scan Fault Coverage With Partial Scan.
DATE 1999: 468-472 |
| 4 | EE | Xijiang Lin,
Irith Pomeranz,
Sudhakar M. Reddy:
Techniques for improving the efficiency of sequential circuit test generation.
ICCAD 1999: 147-151 |
| 3 | EE | Sudhakar M. Reddy,
Irith Pomeranz,
Nadir Z. Basturkmen,
Xijiang Lin:
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.
VTS 1999: 275-283 |
| 1998 |
| 2 | EE | Xijiang Lin,
Irith Pomeranz,
Sudhakar M. Reddy:
MIX: A Test Generation System for Synchronous Sequential Circuits.
VLSI Design 1998: 456-463 |
| 1 | EE | Xijiang Lin,
Irith Pomeranz,
Sudhakar M. Reddy:
On Removing Redundant Faults in Synchronous Sequential Circuits.
VTS 1998: 168-175 |