Oliver Schliebusch

2006
13	EE	Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Automatic ADL-based operand isolation for embedded processors. DATE 2006: 600-605
12	EE	Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum 2006: 233-238
2005
11	EE	Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel: A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC 2005: 280-285
10	EE	Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler: Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation. ICCD 2005: 193-199
9	EE	Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping 2005: 165-171
2004
8	EE	Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl: RTL Processor Synthesis for Architecture Exploration and Implementation. DATE 2004: 156-160
7	EE	Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr: A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1625-1639 (2004)
2003
6	EE	Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr: Instruction encoding synthesis for architecture exploration using hierarchical processor models. DAC 2003: 262-267
5	EE	Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl: Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE 2003: 10966-10973
2002
4	EE	Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann: A universal technique for fast and flexible instruction-set architecture simulation. DAC 2002: 22-27
3	EE	Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr: Architecture Implementation Using the Machine Description Language LISA. VLSI Design 2002: 239-244
2001
2	EE	Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr: A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. ICCAD 2001: 625-630
1	EE	Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr: A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1338-1354 (2001)

Coauthor Index

1	Gerd Ascheid	[8] [9] [11] [12] [13]
2	Gunnar Braun	[1] [2] [3] [4] [5] [6] [7] [8]
3	Michele Cassiano	[12]
4	Anupam Chattopadhyay	[8] [9] [10] [11] [13]
5	Luca Fanucci	[12]
6	B. Geukes	[13]
7	Volker Greive	[6]
8	Andreas Hoffmann	[1] [2] [3] [4] [6] [7]
9	Harold Ishebabi	[13]
10	David Kammler	[9] [10] [11] [12] [13]
11	Tim Kogel	[1] [11]
12	Rainer Leupers	[4] [5] [6] [7] [8] [9] [11] [12] [13]
13	Heinrich Meyr	[1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13]
14	Achim Nohl	[1] [2] [3] [4] [5] [6] [7] [8]
15	Sergio Saponara	[12]
16	Mario Steinert	[8]
17	Oliver Wahlen	[1] [2]
18	Andreas Wieferink	[1] [5]
19	Ernst Martin Witte	[9] [10] [12] [13]