2005 |
5 | EE | V. Kheterpal,
V. Rovner,
T. G. Hersan,
D. Motiani,
Y. Takegawa,
Andrzej J. Strojwas,
Lawrence T. Pileggi:
Design methodology for IC manufacturability based on regular logic-bricks.
DAC 2005: 353-358 |
2004 |
4 | EE | V. Kheterpal,
Andrzej J. Strojwas,
Lawrence T. Pileggi:
Routing architecture exploration for regular fabrics.
DAC 2004: 204-207 |
3 | EE | Aneesh Koorapaty,
V. Kheterpal,
Padmini Gopalakrishnan,
M. Fu,
Lawrence T. Pileggi:
Exploring Logic Block Granularity for Regular Fabrics.
DATE 2004: 468-473 |
2003 |
2 | EE | Lawrence T. Pileggi,
Herman Schmit,
Andrzej J. Strojwas,
Padmini Gopalakrishnan,
V. Kheterpal,
Aneesh Koorapaty,
Chetan Patel,
V. Rovner,
K. Y. Tong:
Exploring regular fabrics to optimize the performance-cost trade-off.
DAC 2003: 782-787 |
2002 |
1 | EE | B. Rajendran,
V. Kheterpal,
A. Das,
J. Majumder,
Chittaranjan A. Mandal,
P. P. Chakrabarti:
Timing analysis of tree-like RLC circuits.
ISCAS (4) 2002: 838-841 |