2006 |
8 | EE | Jeffrey E. Nelson,
Jason G. Brown,
Rao Desineni,
R. D. (Shawn) Blanton:
Multiple-detect ATPG based on physical neighborhoods.
DAC 2006: 1099-1102 |
7 | EE | Jeffrey E. Nelson,
Thomas Zanon,
Rao Desineni,
Jason G. Brown,
N. Patil,
Wojciech Maly,
R. D. (Shawn) Blanton:
Extraction of defect density and size distributions from wafer sort test results.
DATE 2006: 913-918 |
6 | EE | Jeffrey E. Nelson,
Thomas Zanon,
Jason G. Brown,
Osei Poku,
R. D. (Shawn) Blanton,
Wojciech Maly,
Brady Benware,
Chris Schuermyer:
Extracting Defect Density and Size Distributions from Product ICs.
IEEE Design & Test of Computers 23(5): 390-400 (2006) |
2005 |
5 | EE | Brett H. Meyer,
Joshua J. Pieper,
JoAnn M. Paul,
Jeffrey E. Nelson,
Sean M. Pieper,
Anthony G. Rowe:
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors.
IEEE Trans. Computers 54(6): 684-697 (2005) |
2004 |
4 | EE | Alex Bobrek,
Joshua J. Pieper,
Jeffrey E. Nelson,
JoAnn M. Paul,
Donald E. Thomas:
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach.
DATE 2004: 1144-1149 |
3 | EE | Thomas J. Vogels,
Thomas Zanon,
Rao Desineni,
R. D. (Shawn) Blanton,
Wojciech Maly,
Jason G. Brown,
Jeffrey E. Nelson,
Y. Fei,
X. Huang,
Padmini Gopalakrishnan,
Mahim Mishra,
V. Rovner,
S. Tiwary:
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations.
ITC 2004: 508-517 |
2003 |
2 | EE | JoAnn M. Paul,
Alex Bobrek,
Jeffrey E. Nelson,
Joshua J. Pieper,
Donald E. Thomas:
Schedulers as model-based design elements in programmable heterogeneous multiprocessors.
DAC 2003: 408-411 |
1998 |
1 | EE | Ronald F. Brender,
Jeffrey E. Nelson,
Mark E. Arsenault:
Debugging Optimized Code: Concepts and Implementation on DIGITAL Alpha Systems.
Digital Technical Journal 10(1): 81-99 (1998) |