2006 |
12 | EE | Sherief Reda,
Amit Chowdhary:
Effective linear programming based placement methods.
ISPD 2006: 186-191 |
2005 |
11 | EE | Amit Chowdhary,
Karthik Rajagopal,
Satish Venkatesan,
Tung Cao,
Vladimir Tiourin,
Yegna Parasuram,
Bill Halpin:
How accurately can we model timing in a placement engine?
DAC 2005: 801-806 |
10 | EE | Amit Chowdhary,
John P. Hayes:
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 999-1013 (2005) |
2003 |
9 | EE | Sung-Woo Hur,
Tung Cao,
Karthik Rajagopal,
Yegna Parasuram,
Amit Chowdhary,
Vladimir Tiourin,
Bill Halpin:
Force directed mongrel with physical net constraints.
DAC 2003: 214-219 |
8 | EE | Karthik Rajagopal,
Tal Shaked,
Yegna Parasuram,
Tung Cao,
Amit Chowdhary,
Bill Halpin:
Timing driven force directed placement with physical net constraints.
ISPD 2003: 60-66 |
2002 |
7 | EE | Amit Chowdhary,
John P. Hayes:
General technology mapping for field-programmable gate arrays based on lookup tables.
ACM Trans. Design Autom. Electr. Syst. 7(1): 1-32 (2002) |
6 | EE | Amit Chowdhary,
Rajesh K. Gupta:
A Methodology for Synthesis of Data Path Circuitse.
IEEE Design & Test of Computers 19(6): 90-100 (2002) |
1999 |
5 | EE | Amit Chowdhary,
Sudhakar Kale,
Phani K. Saripella,
Naresh Sehgal,
Rajesh K. Gupta:
Extraction of functional regularity in datapath circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1279-1296 (1999) |
1998 |
4 | EE | Amit Chowdhary,
Sudhakar Kale,
Phani K. Saripella,
Naresh Sehgal,
Rajesh K. Gupta:
A general approach for regularity extraction in datapath circuits.
ICCAD 1998: 332-339 |
1997 |
3 | EE | Amit Chowdhary,
John P. Hayes:
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs.
FPGA 1997: 43-49 |
1995 |
2 | EE | Amit Chowdhary,
John P. Hayes:
Technology mapping for field-programmable gate arrays using integer programming.
ICCAD 1995: 346-352 |
1994 |
1 | | Amit Chowdhary,
Dinesh Bhatia:
Detailed Routing of Multi-Terminal Nets in FPGAs.
VLSI Design 1994: 237-242 |